Samsung Electronics Co., Ltd.

Seonghyun Jeon

Wonseok Lee

Dong Hwi Kim

Chankyung Kim

Dong-Hwi Kim

Youngkug Moon

Sangbo Lee

A semiconductor memory device includes a memory cell array of nonvolatile memory cells having a variable resistance element, and a conductor line array capable of generating a compensation magnetic field for the nonvolatile memory cells. A current driver selectively supplies current to conductive lines, a magnetic field sensor senses an applied external magnetic field and generates external magnetic field information, and a controller controls generation of the compensation magnetic field in response to the external magnetic field information.

Semiconductor memory device having variable resistance memory and operating method

A storage device includes a nonvolatile memory device including a variable resistance memory, and a controller configured to control the nonvolatile memory device. At a booting operation, the controller stores booting information in the variable resistance memory of the nonvolatile memory device. At a rebooting operation, the controller selectively performs a warm boot operation using the booting information stored in the variable resistance memory, based on a comparison result between a booting setting condition associated with the booting operation and a rebooting condition associated with the rebooting operation.

Storage device comprising variable resistance memory and related method of operation

A nonvolatile memory includes multiple banks, control logic and multiple read and write (RW) circuits. Each bank includes multiple memory cells. The control logic includes multiple storage units corresponding to the banks, respectively, and configured to output write enable signals and read enable signals to respective banks based on mode information stored in respective storage units. The RW circuits are connected to the banks, respectively, and are configured to independently enable or disable write and read operations of the respective banks in response to the write enable signals and the read enable signals of the respective banks. In an initial state after the mode information is stored in the respective storage units, the control logic activates the write enable signals and the read enable signals of the respective banks regardless of the mode information stored in the respective storage units.

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Seoul, South Korea

Seonghyun Jeon