Korea Advanced Institute of Science and Technology

Skhynix Inc.

SeongHwan Cho

Jin-O Seo

Hyuk-Jin Lee

Seonggyu Lee

Yongjo Kim

Kyunghyun Kim

Kyung Hyun Kim

Hyuk Jin Lee

Hyukjin Lee

Pangi Park

Junseok Hong

Yong-Jo Kim

Jino Seo

Wookon Son

A semiconductor memory device includes a cell array including a plurality of memory cells connected between a first bit line and a source line; a computation control circuit configured to control a first bit line current between the first bit line and the source line during a computation operation; and an output circuit including a first computation capacitor whose charge amount is changed according to the first bit line current during the computation operation, wherein an amount of charge that flows between the first bit line and the source line during the computation operation depends on both data stored in a memory cell among the plurality of memory cells according to a first data and a voltage of a word line connected to the memory cell provided according to a second data.

Semiconductor memory device performing a multiplication and accumulation operation

A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.

Semiconductor device including a memory array performing a multiplication and accumulation (MAC) operation using capacitors

The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.

Band-pass analog-to-digital converter using bidirectional voltage-controlled oscillator

A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.

MAC operating device and method for processing machine learning algorithm

A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

Nonvolatile memory device performing a multiplication and accumulation operation

A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory elements configured to store a plurality of weights and to be controlled according to a plurality of input signals respectively and a bit line coupled to the plurality of nonvolatile memory elements; and a computation output circuit configured to generate a computation signal corresponding to an inner product between an input vector corresponding to the plurality of input signals and a weight vector corresponding to the plurality of weights.

Nonvolatile memory device performing a multiplicaiton and accumulation operation

A semiconductor device includes a cell array, a computation circuit, and a control circuit. The cell array includes a plurality of unit cells configured to store a plurality of first signals by a write operation and to output a plurality of output signals corresponding to the first signals by a read operation. The computation circuit includes a plurality of unit computation circuits receiving the plurality of output signals and being set according to a plurality of second signals during a computation operation. The control circuit is configured to control the cell array and the computation circuit during the write operation, the read operation, and the computation operation.

Semiconductor device performing a multiplication and accumulation operation

A semiconductor device includes a delay circuit configured to adjust a delay amount of multi-phase input signals to output multi-phase signals; a clock generator configured to output a clock signal that is not synchronized with an input signal which corresponds to one of the multi-phase signals; a detector circuit configured to generate a pulse signal corresponding to a phase difference between a reference signal corresponding to a predetermined one of the multi-phase signals and a comparison signal corresponding to a selected one of the multi-phase signals and to sample the pulse signal according to the clock signal; and a controller circuit configured to output a delay control signal for controlling a delay amount of the multi-phase input signals or controlling a delay amount of the comparison signal according to a result of calculating an output of the detector circuit and a reference value corresponding to the phase difference.

Asynchronous clock signal generator and semiconductor device for correcting multi-phase signals using asynchronous clock signal

A semiconductor device includes a first variable delay circuit that delays inputted multiphase signals according to a delay control signal, a selection circuit that selects and outputs two signals of signals output from the first variable delay circuit, a second variable delay circuit that delays one of the two signals according to the delay control signal, a phase comparison circuit that compares a phase of a signal outputted by the second variable delay circuit with a phase of the other of the two signals, a filter that updates the delay control signal according to a signal outputted by the phase comparison circuit, and a delay control signal selection circuit that provides the delay control signal to the first variable delay circuit or the second variable delay circuit.

Semiconductor device

An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL. An all digital phase-locked loop of the present invention includes a digitally controlled oscillator for generating an oscillation signal having a frequency corresponding to an inputted control signal, a re-timer for retiming a reference clock based on the oscillation signal, a feedback circuit for accumulating a number of clocks of the oscillation signal within a time period and generating a phase information of the oscillation signal in synchronization with the retimed reference clock, a sigma-delta modulator for sigma-delta modulating a frequency command signal into a modulation signal having a less number of bits than a number of bits of the frequency command signal, a reference phase accumulator for accumulating phases corresponding to the modulation signal, a phase difference detector for generating a phase difference information between an output signal of the reference phase accumulator and the phase information, and a digital loop filter for filtering the phase difference information to generate the control signal.

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Daejeon, South Korea

SeongHwan Cho