Samsung Electronics Co., Ltd.

Seonghoon Woo

Soon Suk Hwang

Kyuwook Han

Daehyun Kim

Chulseung Lee

Haejong Jang

Haksun Kim

Hong Rak Son

Junjin Kong

Dongjin Park

Jeongil Kang

Pilsang Yoon

Moonyoung Kim

Suhyun Kim

Jaegeun Park

WooSeong Cheong

Daewook Kim

Mankeun Seo

Tae-Eun Park

Taemin Jeong

Soonjae Won

Sang Young Ye

Euihyeok Kwon

Taeeun Park

Yukyeong Kim

Yejin Shin

Donggeun Lim

Hyunsook Lee

Kilhwan Kim

An electronic apparatus includes: a converter including a switching device, an inductor, and an output capacitor; a protection switching device provided between the inductor and the output capacitor; and a protection circuit configured to provide a control voltage to: turn on the protection switching device based on a first voltage applied between the inductor and the protection switching device, the first voltage being lower than or equal to a threshold level corresponding overvoltage, and turn off the protection switching device based on the first voltage, the first voltage being higher than the threshold level. The control voltage is varied depending on variation in the input voltage or the output voltage and having a level corresponding to a threshold voltage for turning on or off the protection switching device.

Electronic apparatus

A memory system may include a plurality of first memory devices; and a memory controller that may include a first chip enable (CE) pin configured to output a first CE signal that enables selectively any one of the first memory devices and a first status input pin configured to receive a first output signal indicating a memory operation status of an enabled first memory device from among the first memory devices in a first memory operation status checking period. In the first memory operation status checking period, the first output signal has one of a first level to indicate a first status of the memory operation status of the enabled first memory device, a second level to indicate a second status of the memory operation status of the enabled first memory device, or a third level to indicate a disabled status of the first memory devices.

Memory systems including memory controllers that use status input pins to check memory operation statuses of memory devices

A storage device is provided. The storage device includes: a plurality of memory devices configured to output status data indicating a busy state indicating an internal operation is being performed or a ready state; and an interface circuit configured to receive a command for reading the status data of the plurality of memory devices, receive the status data of each of the plurality of memory devices from the plurality of memory devices, and output entire status data indicating statuses of the plurality of memory devices based on the status data of each of the plurality of memory devices.

Storage device and method to check statuses of memory devices

An operation method of a storage device connected to a host may include fetching one or more first commands from a first submission queue of the host by performing a first command fetch operation, processing one or more remaining commands other than the last command of the one or more first commands when a last command among the one or more first is a first fused commands, fetching one or more second commands from a second submission queue of the host by performing a second command fetch operation, processing the one or more second commands, and fetching at least two third commands from the first submission queue of the host by performing a third command fetch operation. The at least two third commands may include the first fused command and a second fused command corresponding to the first fused command.

Operation method of storage device

A storage device includes a first memory device, a second memory device, and a controller. The first memory device and the second memory device share the same channel to communicate with the controller. Communication between the first memory device and the controller and communication between the second memory device and the controller are mutually exclusive. When the controller receives a read request directed to the second memory device while the controller processes a direct memory access (DMA) operation directed to the first memory device, the controller suspends the DMA operation and transmits a read command associated with the read request to the second memory device.

Storage device temporarily suspending internal operation to provide short read response time for read request from host

A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.

Controller and storage device including controller and nonvolatile memory devices

A storage device includes a controller and a nonvolatile memory device. The controller includes a field programmable gate array (FPGA) and receives an FPGA image for updating the FPGA from an outside in response to a first command received from the outside. The nonvolatile memory device stores the FPGA image. The controller receives the FPGA image through a main interface or a sideband interface, and executes the FPGA image in response to a second command received from the outside.

Storage device configured to update field programmable gate array and method of operating the same

A storage device includes a plurality of nonvolatile memories and a controller. The plurality of nonvolatile memories are configured to distributively store first and second stripes of a stripe set. The controller includes a first memory and a second memory within the controller. The controller is configured to receive the first and second stripes from a host, distributively store the first and second stripes in the plurality of nonvolatile memories, and to perform a parity operation based on the first and second stripes. The controller is configured to generate intermediate parity based on the first stripe and store the intermediate parity in the first memory. If the parity operation is stopped, the controller is configured to move the intermediate parity stored in the first memory to the second memory.

Storage device storing data in raid manner

A storage device includes a nonvolatile memory device, and a controller configured to control the nonvolatile memory device based on metadata. The controller encrypts the metadata and loads the encrypted metadata on a random access memory of an external host device.

Storage device and operating method of storage device

A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of signal processing engines; and a decoding scheduler configured to control a data path such that at least one activated signal processing engine of the plurality of signal processing engines is connected with the plurality of channels, respectively.

Memory controller and memory system including the same

A memory controller comprises a host interface block comprising a compression ratio calculator configured to determine whether a compression ratio of input data exceeds a predetermined compression ratio, and a compression block configured to compress the input data as a consequence of the host compression ratio calculator determining that the compression ratio exceeds the predetermined compression ratio.

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Hwaseong-si, South Korea

Seonghoon Woo