Samsung Electronics Co., Ltd.

Seonggwon Jang

Yongjeong Kim

Sooyong Park

Ungjin Jang

Jongjin An

Pilho Lee

Inhoon Jang

A test device configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation includes a logic generation/determination device configured to generate multiple bits corresponding to a test pattern, first and second drivers configured to generate respective first and second non return to zero (NRZ) signals according to a logic state of respective first and second bits among the multiple bits and output the respective generated first and second NRZ signals via respective first and second channels. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first and second high levels are different from each other.

Test devices, test systems, and operating methods of test systems

Provided are a clock conversion device, a test system including the same, and a method of operating the test system. The clock conversion device includes a first clock generator configured to receive a first input clock signal from test logic and generate a first clock signal of which a frequency is multiplied and a phase is locked; a clock conversion circuit configured to receive the first clock signal and generate one or more second clock signals by converting at least one clock characteristic of the first clock signal; and an output selector configured to output any one of the first clock signal and the one or more second clock signals as an output clock signal, wherein the clock conversion device is configured to provide the output clock signal to a device under test (DUT).

Clock conversion device, test system having the same, and method of operating test system

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Asan-si, South Korea

Seonggwon Jang