Skhynix Inc.

Korea University Research and Business Foundation

Seong Yoon Kang

Jong Sun Park

Myeong Jae Park

Byung Kuk Yoon

Mun Seon Jang

Jun Il Moon

Sang Uhn Cha

A memory system may include a memory core; and an ECC engine configured to, during a write operation, perform a logical operation on an M-bit write data and an H matrix, and generate an N-bit first error correction code and an N-bit second error correction code to be stored in the memory core together with the write data, where N is an integer of 2 or more and M is a multiple of N. The H matrix may include an upper matrix having a size of N*(M+2N) and a lower matrix having a size of N*(M+2N), the lower matrix may include M/N Tcompanion matrices each having a size of N*N, and k of the Tcompanion matrices may have values which are positive integers different by N or more for each companion matrix.

Memory system including ECC engine

Disclosed are a bus inversion encoder module that utilizes future data in a data bus including a serializer with minimum latency and high transition reduction efficiency by comparing current data with both past data and the future data and encoding the current data, and a bus inversion system including the same. The bus inversion encoder module uses current data, past data, and future data transmitted through a bus and each including a plurality of bits, determines whether to invert the current data, and generates a current flag and coded current data by using whether to invert, an output flag, and the current data. The output flag is generated by summing the current flag and the coded current data and serially converting the current flag and the coded current data.

Bus inversion encoder module and bus inversion system including the same

Growing community of inventors

Seoul, South Korea

Seong Yoon Kang