Samsung Electronics Co., Ltd.

Seong Woon Kim

Sang Hoon Lee

Sung Chul Yoon

Kil Whan Lee

Kwan Ho Kim

Ha Na Yang

Tae Sun Kim

Seok Min Kim

Sang Hoon Ha

Sun-Ae Kim

Yong Kwon Cho

Hyeong-Seok Kim

Kwanho Kim

Kyoungmook Lim

Sang Chul Yoon

Jae-Deok Nam

Kyoung Mook Kim

A system on chip and a mobile device are provided, the mobile device including a processor that receives raw image data, processes the raw image data into floating-point format image data, and output the floating-point format image data; a memory that stores therein the floating-point format image data; and a display processing unit that receives the floating-point format image data stored in the memory therefrom, and performs high dynamic range (HDR) processing on the floating-point format image data.

System on chip and mobile device including the same

A display controller includes a resource controller configured to receive layer information about each of a first layer and a second layer that are output at different times through a display panel during a unit frame. The display controller includes a data input direct memory access (DMA) configured to receive first image data corresponding to the first layer and second image data corresponding to the second layer, and a hardware resource configured to receive the first and second image data from the data input DMA, process the received first and second image data according to the layer information, and generate first layer data of the first layer and second layer data of the second layer. The resource controller is configured to control the data input DMA according to the layer information to determine an order in which the first and second image data are provided to the hardware resource.

Display controller and display device including the same

A semiconductor device includes a processor configured to perform a rendering operation of an image frame to acquire rendering data, and write the acquired rendering data on a memory device, and a display controller configured to perform a read operation of the memory device on which the rendering data is written, to acquire image data. The semiconductor device further includes a micro-sequencing circuit configured to transmit a start signal to the display controller, based on a degree of execution of the rendering operation. The display controller is further configured to, based on the transmitted start signal, start the read operation.

Semiconductor device

An image processor, an application processor, a method of operating an image processor, and a chips set of an image processor are provided. The image processor includes a scaler configured to perform scaling on an input image and generate a scaled input image; and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal. The application processor includes a memory configured to store an input image; and an image processor configured to scale the input image, wherein the image processor comprises a scaler configured to perform scaling on the input image and generate a scaled input image and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal.

Image processor, method, and chipset for increasing intergration and performance of image processing

An application processor includes a first scaler including a first vertical scaler and a first horizontal scaler, and a second scaler including a second vertical scaler and a second horizontal scaler, wherein the second vertical scaler is selectively shared between the first scaler and the second scaler in response to a determination of resolution for an image being processed.

Application processor sharing resource based on image resolution and devices including same

A image processing method includes computing an initial phase corresponding to a difference between a position of a first pixel of an input image and a position of a first pixel of an output image using at least one of scaling ratio information between the input and output images, chroma subsampling format conversion information applied between the input and output images, or rotation angle information of the input image, and determining the position of the first pixel of the output image based on the initial phase and the position of the first pixel of the input image.

Image processing device for computing an initial phase having magnitude and direction based on image processing information

A system on chip (SoC) including a memory management unit (MMU) and a memory address translation method thereof are provided. The SoC includes a master intellectual property (IP) configured to output a request corresponding to each of a plurality of working sets; an MMU module comprising a plurality of MMUs, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the MMU module with a memory device and to transmit the request, on which address translation has been performed in at least one of the MMUs, to the memory device; and a second bus interconnect configured to connect the master IP with the MMU module and to allocate one of the MMUs for each of the working sets.

System on chip including memory management unit and memory address translation method thereof

A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address. The method also includes reading data from a data buffer among a plurality of data buffers included in the first storage device using a physical address included in the entry and transmitting the data to the second storage device.

Integrated circuit for computing target entry address of buffer descriptor based on data block offset, method of operating same, and system including same

A method of encoding/decoding data for storage and retrieval from a flash memory device, by generating a first error correction code on a combination of first user data to be stored in a first logical unit of storage in the flash memory device and padding data derived from second user data and an associated second error correction code stored in a second logical unit of storage in the flash memory device. The first user data and the first error correction code can be stored in the first logical unit of storage.

Growing community of inventors

Suwon-si, South Korea

Seong Woon Kim