Magnachip Semiconductor, Inc.

Seong Woo Lee

Hee Baeg An

Francois Hebert

Young Joon Kim

Kang Sup Shin

Jong Yeul Jeong

Seong Min Choe

Jae Hyung Jang

Yu Shin Ryu

There is provided a hall sensor. The hall sensor includes a hall element disposed on a semiconductor substrate. The hall element includes: a sensing region, a first electrode, a second electrode, a third electrode and a fourth electrode, and a doped region disposed on the sensing region, and the sensing region has at least one angulated corner or rounded corner.

Semiconductor-based hall sensor

A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing area comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

Semiconductor device having circuitry positioned above a buried magnetic sensor

A semiconductor device including a circuitry, a magnetic sensor, and a buried oxide. The circuitry is formed on a substrate. The magnetic sensor has a sensing area formed under the circuitry. The buried oxide is disposed between the circuitry and the magnetic sensor. The sensing are comprises an N-doped area and a P-doped area doped deeper than the N-doped area, and sensor contacts connect the sensing area with the circuitry through the buried oxide.

A Hall sensor with improved doping profile is disclosed. The Hall sensor includes a semiconductor substrate, a sensing region formed on the substrate, an isolation region formed on the sensing region, and a high concentration doping region formed on an upper portion of the sensing region.

Hall sensor with improved doping profile

Disclosed herein is a parallel capacitor of a semiconductor device. According to the present invention, a first capacitor and a second capacitor are formed in different layers of the same region, wherein a metal layer connected to an upper electrode of the first capacitor is formed in the same layer as a metal layer connected to a lower electrode of the second capacitor. Thus, twp capacitors can be connected in parallel only with a metal layer composed of three layers. Accordingly, the present invention is advantageous in that it can reduce process steps for forming multiple metal layers, lower a step and cut manufacture cost.

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Cheongju-si, South Korea

Seong Woo Lee