Skhynix Inc.

Seong Won Shin

Young Tack Jin

Sungjoon Ahn

Yi Tong

Jeffrey Song

Seungwan Jung

Kyoungsun Hong

Kailash Mallikarjunaswamy

A method for operating a system including a host and at least one solid state drive (SSD). The method identifies a workload associated with the SSD, recognizes a power state of the SSD, and controls allocation and/or deallocation of hardware resources for the identified workload per a budgeted target for the power state.

SSD performance per power state improvement by deterministic utilization control

Disclosed is a method of allocating a buffer memory to a plurality of data storage zones. In some implementations, the method may include comparing a free buffer space size to a reallocation threshold size that is re-allocable at a reallocation cycle, deallocating, upon a determination that the free buffer space size is smaller than the reallocation threshold size, at least a portion of an occupied buffer space size to create a new free buffer space based on a history of buffer memory utilization of the occupied buffer space, and allocating the existing free buffer space and the new free buffer space to targeted data storage zones based on history of buffer memory utilizations corresponding to the targeted data storage zones.

Utilization based dynamic shared buffer in data storage system

A controller of a memory system controls a completion rate of commands. The controller receives, from a host, command requests to be processed on a memory device. The controller processes the command requests, determines a first number of completion notifications, which are to be transmitted to the host in a first time interval, among multiple completion notifications associated with the command requests, based on a throughput credit, a set maximum credit, and the number of the multiple completion notifications. The controller transmits, to the host, the first number of completion notifications in the first time interval, and transmits a second number of completion notifications in the second time interval.

Systems and methods for controlling completion rate of commands

A data processing system includes a host device and a memory system including a controller and a memory device. The controller receives a command for the memory device from the host device, determines whether at least one slowdown event occurs due to an internal operation, and when it is determined that the slowdown event occurs, notifies the host device of occurrence of the slowdown event.

System for slowdown status notification and operating method thereof

A memory system and an operating method thereof include: at least a CPU including multiple CPU cores, wherein the multiple CPU cores include reserved CPU cores and host CPU cores; at least a PCIe link coupled with the CPU, wherein the PCIe link includes at least a PCIe switch and a plurality of memory devices; and the plurality of memory devices coupled with the host CPU cores through respective workload threads and interrupt handlers, wherein the workload threads and interrupt handlers of each of the host CPU cores are configured to be optimized, the host CPU cores are isolated for the optimized workloads threads and interrupt handlers, and the workload threads and interrupt handlers are executed at the host CPU cores coupled thereto.

Memory system with latency distribution optimization and an operating method thereof

A data processing system includes a host device and a memory system including a plurality of units. The host device includes a workload generation component and an analysis component. The workload generation component concurrently transmits, to the memory system, a plurality of commands for the plurality of memory units. The analysis component receives, from the memory system, command completion messages corresponding to the plurality of commands; measures latencies of the plurality of commands based on the receiving of the command completion messages; and analyze a parallelism scheme of the plurality of memory units based the measured latencies.

System and method for discovering parallelism of memory devices

A storage node includes a storage element module. The module includes a first peripheral component interconnect express (PCIe) switch suitable for uplink connection, a second PCIe switch coupled to the first PCIe switch, and at least one connection element coupled to the second PCIe switch, suitable for coupling with at least one storage element. All PCIe end point elements and uplink connection elements are in a PCIe card form factor as defined in PCI Express Card Electromechanical Specification.

Storage node based on PCI express interface

A peripheral component interconnect express (PCIe) card may include a base card, a mezzanine card and mezz connectors. The base card may be coupled to a host device, and host a first group of solid state drives (SSDs). The mezzanine card may be stacked over the base card, and host a second group of SSDs. The mezz connectors may couple the base card with the mezzanine card, each of the mezz connectors corresponding to each of the second group of SSDs. The base card may include an edge connector suitable for coupling with the host device, a PCIe switch suitable for coupling the first and second groups of SSDs with the host device through the edge connector, and a first group of connectors suitable for coupling the first group of SSDs with the PCIe switch. The mezzanine card may include a second group of connectors suitable for coupling the second group of SSDs.

Growing community of inventors

San Jose, CA, United States of America

Seong Won Shin