Samsung Electronics Co., Ltd.

Seoul National University

Seong-won Lee

Jae-sung Lee

Joon-Ki Paik

Soo-Mook Moon

Sang-Hyeon Baeg

Je-hyung Lee

Gyu-young Kim

Nam-cheol Kim

Jin-pyo Lee

Jin-seok Oh

Won-ki Jung

A method and an apparatus for dynamically generating a machine code is provided, including: sequentially storing generated instructions in a first buffer; sequentially storing data in a second buffer, when the generated instructions reference data; and flushing the first buffer and the second buffer to executable code when a distance between an instruction referencing the data and the data has reached a limit of an offset range of the data-referencing instruction.

Method and apparatus for dynamically generating machine code

An test circuit and method for testing an integrated device having an embedded function and a built-in test circuit for testing the embedded function. The built-in test circuit provides control signals to the embedded function based upon an internal state of the built-in test circuit. The integrated device is tested by comparing the control signals provided to the embedded function to the desired control signals based upon the internal state of the built-in self test circuit to confirm the proper operation of the built-in self test circuit. The internal state of the built-in test circuit is monitored and the control signals provided to the embedded function are monitored. The monitored signals are compared to an expected signal pattern based upon the monitored internal state of the built-in test circuit. An error signal is generated if the comparison determines that the monitored control signals do not correspond to the expected signal pattern.

Test circuits and methods for built-in testing integrated devices

Disclosed is a syntax parser for a video decoder for MPEG2 and includes: a shift register which executes the shift operation after receiving MPEG video bitstream; a ROM which stores a program decoding variable length and controlling the hardware operation, and outputs the micro-instruction according to an address; a counter which controls the address of the ROM; a register which stores parameters for decoding MPEG video; a flag controller which generates the flag from a particular code included in the bitstream or the combination of parameters, and outputs the flag; a memory which stores the table related to variable length decoding; and a length controller which gets length information to be shifted from the memory, the micro-instruction or the output of the register. The syntax parser for a MPEG2 video decoder can execute VLD and parse the MPEG bitstream. Using micro-instructions to perform the parsing function decreases the decoding time for the bitstream and obtains the parsing speed corresponding to the MP@HL of the HDTV (high definition television) standard.

Syntax parser for a MPEG2 video decoder

A video decoder that operates according to MPEG (Moving Picture Experts Group) standards. The video decoder includes a parsing stage including inverse quantization and run-length decoding. An inverse transform stage and a compensating stage are then performed. Run-length decoding is performed just prior to the inverse transform stage and after the inverse quantization reducing the total number of pipelines and reducing the number of buffers.

MPEG video decoder

A semiconductor wafer label for identifying a wafer includes at least one concave mark formed on an edge of a flat zone of each wafer. The label may include one or more concave marks having a first width and first length and one or more concave marks having a second width and a second length. Accordingly, it is not necessary to take the wafer out of a wafer cassette in order to read the wafer number, thereby reducing contamination and damage to the wafer.

Label for semiconductor wafer

A method of interpolating digital image data includes steps for calculating an absolute value of the difference between two neighboring pixels of image data, among four neighboring pixels of image data, determining maximum and second-most maximum values among the thus-calculated absolute values and interpolating the image data using the results. An interpolation circuit for performing above-described method includes an edge detector, a pre-filter, a zero-order interpolation area controller, a zero-order interpolator, a movement averaging device, a magnification factor controller and a post-filter.

Growing community of inventors

Seoul, South Korea

Seong-won Lee