Samsung Electronics Co., Ltd.

Seoul National University

Seong-won Kim

Sung-hyun Choi

Min-kyu Song

Geun-Soon Kang

Eu-Ro Joe

Jin-Woo Yang

Chul-Hoon Hwang

Kang-hyun Lee

Ji-Woo Jeong

Young-wook Son

Seung-Min Yoo

Jong-hun Han

Yeon-Chul Shin

Seo-Min Yang

Provided is a wireless communication device including at least one processor configured to transmit a plurality of test signals generated based on different transmission factors to a reception device, and transmit first data to the reception device based on a transmission factor of a first test signal among the plurality of test signals in response to determining a first acknowledgement signal has been received, the first acknowledgement signal corresponding to the first test signal, the transmission of the first data being via a wireless data channel while second data is contemporaneously transmitted via the wireless data channel by another device.

Wireless communication devices for transmitting data using spatial reuse and data communication methods using the same

A method and an apparatus for performing transmission power selection of a wireless access device and channel allocation in a combination manner, for resource management optimized for a wireless network environment supporting multimedia traffic are provided. In a method for managing a radio resource of at least one Access Point (AP) in a wireless communication network, a transmission power select operation for the AP is performed on each of a plurality of channel settings, and a network performance value is predicted. Optimized channel setting is selected among the plurality of channel settings depending on the predicted network performance value. The optimized channel setting and optimized transmission power corresponding to the optimized channel setting are allocated to the AP.

Method and apparatus for managing radio resource in wireless communication system

Energy economized pass-transistor logic circuit and full adder using the

A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

CMOS output buffer circuit exhibiting reduced switching noise

Growing community of inventors

Seoul, South Korea

Seong-won Kim