Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Seong Soon Cho

Sung-Hun Lee

Kwang Soo Seol

Chang-Sup Lee

Joonhee Lee

Jintae Kang

Jeehoon Han

Sunghoi Hur

Taekyung Kim

Seokjung Yun

Minchul Kim

Jiyoung Kim

Jintaek Park

Jinhyun Shin

Seungwook Choi

Ji Hye Kim

Kyung-hun Lee

Jahun Koo

Jin-Soo Lim

Hongsoo Kim

Jee-Hoon Han

Dongseog Eun

Byoungil Lee

Jongwoon Kim

Kyung Jun Shin

Seok-Jung Yun

Hyunchul Back

Byungjoo Go

Kyung-Jun Shin

Yong-Won Chung

Jae Joo Shim

Kim Taekyung

Hyunkook Lee

Seungwook Chol

A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Three-dimensional semiconductor memory device with increased process margin

A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

Three-dimensional semiconductor device

A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Semiconductor device, systems and methods of manufacture

Three-dimensional semiconductor memory device including an electrode connecting portion

A display device includes a backlight unit including light source rows, each of the light source rows including light source blocks, a display panel configured to display an image by transmitting light emitted by the backlight unit, a panel driver configured to drive the display panel, and a backlight driver configured to drive the backlight unit. The backlight driver is configured to perform a vertical direction scan operation that sequentially select the light source rows and a horizontal direction sequential driving operation that sequentially drives the light source blocks included in a selected light source row of the light source rows.

Display device performing local dimming

Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers. The semiconductor device includes a dummy cell region. The semiconductor device includes a plurality of bit lines and a plurality of auxiliary bit lines. Some of the plurality of auxiliary bit lines have different respective lengths. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including auxiliary bit lines

Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n-1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n-1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Vertical memory devices including stacked conductive lines and methods of manufacturing the same

A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Vertical memory device

Three-dimensional semiconductor memory device including stacked electrodes having pad portions

Growing community of inventors

Suwon-si, South Korea

Seong Soon Cho