Samsung Electronics Co., Ltd.

Seong-Soo Lee

Yong-jin Kim

Jae-Seung Son

Young-Eil Kim

Kyoung-Sub Shin

Young-Hwan Kim

Jae-Seung Hwang

Hyuncheol Park

Mi-Hyun Son

Do-hoon Kwon

Sang-Min Han

Jae-Hyon Kim

Gyung-Jin Min

Jung-Ik Oh

Suk-Ho Joo

Byung-Tae Yoon

Joonhyuk Kang

Dae-Hyun Jang

Yong-Hyun Kwon

Ki-Jeong Kim

Yoo-Chul Kong

Jae-ho Min

Han-Na Cho

Hyunkuk Kim

Han-Geun Yu

Yung-Il Kim

Se-Hyun c/o Samsung Adv Inst Of Technology Park

A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

Method of forming a step pattern structure

According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths.

Methods of manufacturing a vertical type semiconductor device

Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask.

Method of forming a micro-pattern for semiconductor devices

A method of manufacturing a semiconductor device comprises forming memory cells on a memory cell region, alternately forming a sacrificial layer and an insulating interlayer on a connection region for providing wirings configured to electrically connect the memory cells, forming an etching mask pattern including etching mask pattern elements on a top sacrificial layer, forming blocking sidewalls on either sidewalls of each of the etching mask pattern element, forming a first photoresist pattern selectively exposing a first blocking sidewall furthermost from the memory cell region and covering the other blocking sidewalls, etching the exposed top sacrificial layer and an insulating interlayer to expose a second sacrificial layer, forming a second photoresist pattern by laterally removing the first photoresist pattern to the extent that a second blocking sidewall is exposed, and etching the exposed top and second sacrificial layers and the insulating interlayers to form a staircase shaped side edge portion.

Methods of manufacturing a semiconductor device and a semiconductor memory device thereby

After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal wiring structure is formed on the recessed plug and on the insulation layer. A lower portion of the metal wiring structure, formed within the contact hole, prevents damage to the recessed plug during an etching process for forming the metal wiring structure. Therefore, the recessed plug may be formed without damage thereof even if an alignment error occurs between an etching mask and the recessed plug during metal wiring structure formation.

Semiconductor device having a metal wiring structure

A planar antenna manufactured by patterning a substrate consisting of a dielectric layer, and first and second conductive layers applied, respectively, to both opposite surfaces of the dielectric layer. A first slot is formed in the first conductive layer for radiating electric waves. A second slot is formed in the first conductive layer for intercepting a particular frequency of the electric waves radiated by the first slot. A power supply portion is formed with the first conductive layer for supplying electric current to the first slot. A radiating element formed with the second conductive layer, which is excited by the electric waves radiated by the first slot, and radiates the electric waves.

Ultra-wideband planar antenna having frequency notch function

In a method for shallow trench isolation and a method for manufacturing a non-volatile memory device using the same, a hard mask layer pattern, a stopper layer pattern and an oxide film pattern are formed by patterning a hard mask layer, a stopper layer and an oxide film. A trench is formed by etching an upper portion of a substrate adjacent to the stopper layer pattern with the hard mask layer pattern. After removing the hard mask layer, a field oxide layer is formed in the trench. After etching the trench with the hard mask, the aspect ratio of the trench region is reduced by removing the hard mask prior to filling the trench, enhancing the gap filling margin of the trench fill process.

Shallow trench isolation method and method for manufacturing non-volatile memory device using the same

Disclosed is a radio frequency filter of a combline structure including a frequency cut-off circuit for cutting off a specific frequency from a frequency band having a given frequency bandwidth. The frequency cut-off circuit includes an inductive transmission line extending from the output terminal by a length determined to provide an approximate inductance corresponding to a calculated value approximate to an inductance for obtaining the specific frequency, and a capacitive element coupled to the approximate inductance provided by the inductive transmission line, so that it has a capacitance for obtaining the specific frequency. The inductive transmission line is connected to the capacitive element through a via hole formed at an end of the transmission line opposite to the output terminal, from which the transmission line extends. The invention also proposes a method for implementing the radio frequency filter.

Radio frequency filter of combline structure having frequency cut-off circuit and method for implementing the same

Growing community of inventors

Seongnam-si, South Korea

Seong-Soo Lee