Sun Microsystems, Inc.

Seong Rai Cho

Yet-Ping Pai

Dae Suk Jung

Yu-Yen Mo

Manoj Gopalan

Venkat R Podduturi

A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Hierarchical repeater insertion

One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

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San Jose, CA, United States of America

Seong Rai Cho