Yonsei University

Samsung Electronics Co., Ltd.

Seong Ook Jung

Tae Woo Oh

Se Hee Lim

Se Keon Kim

Dong Han Ko

Tae Hyun Kim

Ju Hyun Park

Hong Keun Ahn

Su Min Lee

Han Wool Jeong

Sung Hwan Joo

Dong Hwan Lee

Won Seok Lee

Taejoong Song

Jung Hyun Park

Jong-Ryun Choi

Jong Ha Park

Woojin Rim

Byung Kyu Song

Hanwool Jeong

Gyuhong Kim

Alex Joo

Ki Ryong Kim

Dong Hoon Jung

Young Kyu Lee

Se Hyuk Oh

Kyeong Ho Ryu

Hee Chai Kang

Min June Yeo

Ji Sang Oh

Keon Hee Cho

In Jun Jung

An SRAM comprises: a memory cell array in which a plurality of memory cells each defined by a word line and a bit line pair are arranged; a write driver that applies a write voltage corresponding to the applied data to a bit line pair connected to the memory cell; and a word line driver activating the word line after the write voltage is applied to the bit line pair and after a pre-develop period.

SRAM with improved write performance and write operation method thereof

A content addressable memory based on a self-rectifying ferroelectric tunnel junction element comprises: a cell array unit having a plurality of TCAM cells, each comprising two self-rectifying ferroelectric tunnel junction elements (SR-FTJ) connected between a corresponding match line of a plurality of match lines extending in a first direction and a corresponding bit line pair of a plurality of bit line pairs extending in a second direction; a precharge unit precharging a corresponding match line of the plurality of match lines to a power supply voltage level in response to a precharge signal; and a data input/output unit having a plurality of access transistor pairs electrically connecting or disconnecting a corresponding bit line pair among the plurality of bit line pairs and a source line, in response to a voltage applied through a corresponding search line pair among a plurality of search line pairs according to data to be written or searched.

Content addressable memory based on selfrectifying ferroelectric tunnel junction element

A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.

Bit line sense amplifier and semiconductor memory apparatus using the same

Exemplary embodiments provide a sensing amplifier based flip-flop applying a nonvolatile memory device which is applicable to a mobile device which has a small hardware area, uses a small control signal, does not include a separate write circuit, has low writing power consumption, a short reading time and small power consumption, and requires a low power operation.

Ferroelectric FET nonvolatile sense-amplifier-based flip-flop

A nonvolatile memory device according to the embodiment includes: a first inverter; and a second inverter cross-coupled to the first inverter, wherein the second inverter includes a pull-up transistor, a pull-down transistor, and a ferroelectric field effect transistor having gate nodes connected to each other, and a restore transistor having one electrode connected to the ferroelectric field effect transistor, and the second inverter stores data in a nonvolatile manner.

Nonvolatile memory device and latch including the same

A PUF apparatus comprises: a PUF cell array in which a plurality of PUF cells are arranged each including a FeFET pair whose gates are commonly connected to a corresponding word line among a plurality of word lines, and whose drains and sources are connected to a corresponding bit line pair and a corresponding source line pair among a plurality of bit line pairs and a plurality of source line pairs running in a direction crossing the plurality of word lines; and a read-write-back block which is activated according to a read enable signal, and senses and amplifies a voltage difference occurring in a corresponding bit line pair among the plurality of bit line pairs according to the difference in driving strength due to a deviation in a manufacturing process of the FeFET pair in the PUF cell selected by a selected word line among the plurality of word lines.

Physically unclonable function apparatus based on ferroelectric elements and operation method thereof

Disclosed is an in-memory device for operation of a multi-bit weight. A multi-bit memory cell array according to an exemplary embodiment of the present invention includes at least one multi-bit unit which stores input data based on an input signal and outputs a per-group sum value summed for every group by applying a multi-bit weight to the stored input data; and a final summation unit which is connected to at least one multi-bit unit, adjusts a ratio for every group to receive the peer-group sum value, and outputs a final output value by summing the input per-group sum value.

In-memory device for operating multi-bit weight

A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.

Ferroelectric random access memory device and method for operating read and write thereof

A method for optimizing a hardware structure of a convolutional neural network including: searching an initial feature value group by which a final convolution layer located at a final stage among a plurality of convolution layers, setting an initial fusing network by analyzing a feature value group having a size corresponding to the initial feature value group; computing an operation time for each layer by allocating the number of operators corresponding to the size of the feature value group to each of the plurality of convolution layers, and dividing the size of the feature value group by determining a layer having a minimum operation time; resetting the fusing network by changing the size of the feature value group, determining the size of the feature value group having the smallest number of operators, determining the number of operators to be included in each of the plurality of convolution layers.

Method for optimizing hardware structure of convolutional neural networks

Disclosed is a memory device for cancelling a sneak current. The memory device according to the exemplary embodiment of the present disclosure includes a memory cell array which includes a plurality of word lines and a plurality of bit lines intersecting each other and memory cells disposed at intersections of the word lines and the bit lines; and a sensing circuit which supplies a bit line current to all or some of the bit lines, cancels a sneak current based on the bit line current by at least one switching control, and senses and amplifies data stored in the memory cell to output the sensed and amplified data.

Memory device for canceling sneak current

Disclosed is an image upscaling apparatus that includes: multiple convolution layers, each configured to receive an input image or a feature map outputted by a previous convolution layer and extract features to output a feature map; and a multilayer configured to receive a final feature map outputted from the last convolution layer and output an upscaled output image. The multilayer includes: a first partition layer including first filters having a minimum size along the x-axis and y-axis directions and the same size as the final feature map along the z-axis direction; and at least one second partition layer, each including second filters, having a size greater than that of the first filter in the x-axis and y-axis directions and having a number and size of the first filter in the z-axis direction, and configured to shuffle features in the x-axis and y-axis directions of the first shuffle map.

Image upscaling apparatus using artificial neural network having multiple deconvolution layers and deconvolution layer pluralization method thereof

An apparatus for harvesting energy includes an AC harvester having an AC harvesting capacitor and configured to extract power from an AC environment energy source, a DC harvester configured to extract power from a DC environment energy source, and a power transferrer configured to control a transfer path of power extracted from the DC harvester based on a magnitude of a voltage of the AC harvesting capacitor and a magnitude of a voltage applied from the DC harvester.

Apparatus for harvesting energy using dual environment energy source and method thereof

Disclosed are an apparatus for measuring distance using two-step tracking and a method thereof. More particularly, the apparatus includes a bit generator configured to generate coarse bits for first tracking from sensing data to measure distance to a target and fine bits for second tracking, corresponding to the coarse bits, to measure precise distance to the target; a coarse bit processor configured to receive the coarse bits, address the received coarse bits in any one histogram bin, which corresponds to the received coarse bits, among a plurality of histogram bins, and output coarse bits, which correspond to any one histogram bin exceeding a preset threshold among the histogram bins, as reference coarse bits; and a fine bit processor configured to output fine bits corresponding to the reference coarse bits.

Apparatus for measuring distance using two-step tracking based on SPAD sensor and method thereof

Disclosed is a static random access memory including an assist circuit. More particularly, a static random access memory according to an embodiment of the present disclosure may include a bit cell part including at least one bit cell connected between a first ground voltage node and a second ground voltage node; and a controller including a first transistor configured to control connection between the first ground voltage node and the second ground voltage node, a second transistor configured to float a first ground voltage of the first ground voltage node, and a third transistor configured to float a second ground voltage of the second ground voltage node, wherein the controller controls the first and second ground voltages supplied to the bit cell part using the first, second, and third transistors.

Static random access memory including assist circuit

Disclosed is an SRAM cell capable of performing a differential operation. An SRAM cell according to an embodiment of the present disclosure may include a data node portion including four transistors constituting first and second data nodes; a data controller including first and second pass-gate transistors configured to control read and write of data in the first and second data nodes; and a control transistor connected to the data node portion through the second data node and configured to be controlled based on a driving voltage of a second word line having an opposite polarity to a first word line transmitting a driving voltage to the data controller.

Growing community of inventors

Seoul, South Korea

Seong Ook Jung