Samsung Electronics Co., Ltd.

Seoul National University

Lg Electronics Inc.

Sungkyunkwan University

Nhn Corporation

Seong-jun Park

Jin-seong Heo

David Seo

Hyun-jong Chung

Hyun-Jae Song

Kyung-Eun Byun

Jae-ho Lee

Hyeon-jin Shin

Hee-jun Yang

Sang-Wook Kim

Chang-seung Lee

Hyung-cheol Shin

Jae-hong Lee

Young-jun Yun

Chang-jung Kim

In-kyeong Yoo

Myoung-jae Lee

Dong-Soo Lee

Young-Bae Kim

Chang-bum Lee

Man Chang

Seung-ryul Lee

Yun-sung Woo

Ji-hyun Hur

Yung-hee Yvette Lee

Seong-jun Jeong

Sun Young Park

Ho-jung Kim

Dong Wook Lee

Hyoung-sub Kim

Young-hee Lee

Dong-Wook Lee

Mi Suk Eom

Kuk-Jin Kang

Yea-hyun Gu

Yangji Kim

Jeongsang Lee

Jae-hyun Yang

Hyun Jung Moon

Ji Woon Jung

Su Ryun Shin

Min-Hyun Lee

Example embodiments relate to a stacking structure having a material layer formed on a graphene layer, and a method of forming the material layer on the graphene layer. In the stacking structure, when the material layer is formed on the graphene layer by using an ALD method, an intermediate layer as a seed layer may be formed on the graphene layer by using a linear type precursor.

Stacking structure having material layer on graphene layer and method of forming material layer on graphene layer

A thin film structure includes a metal seed layer, and a method of forming an oxide thin film on a conductive substrate by using the metal seed layer is disclosed. The thin film structure includes a transparent conductive substrate, a metal seed layer that is deposited on the transparent conductive substrate, and a metal oxide layer that is deposited on the metal seed layer.

Thin film structure including metal seed layer and method of forming oxide thin film on transparent conductive substrate by using the metal seed layer

A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.

Memory device using graphene as charge-trap layer and method of operating the same

Inverters including two-dimensional (2D) material, methods of manufacturing the same, and logic devices including the inverters. An inverter may include a first transistor and a second transistor that are connected to each other, and the first and second transistor layers may include 2D materials. The first transistor may include a first graphene layer and a first 2D semiconductor layer contacting the first graphene layer, and the second transistor may include a second graphene layer and a second 2D semiconductor layer contacting the second graphene layer. The first 2D semiconductor layer may be a p-type semiconductor, and the second 2D semiconductor layer may be an n-type semiconductor. The first 2D semiconductor layer may be arranged at a lateral side of the second 2D semiconductor layer.

Inverter including two-dimensional material, method of manufacturing the same and logic device including inverter

A graphene device and an electronic apparatus including the same are provided. According to example embodiments, the graphene device includes a transistor including a source, a gate, and a drain, an active layer through which carriers move, and a graphene layer between the gate and the active layer. The graphene layer may be configured to function both as an electrode of the active layer and a channel layer of the transistor.

Graphene device and electronic apparatus

Disclosed are memory devices including a two-dimensional (2D) material, methods of manufacturing the same, and methods of operating the same. A memory device may include a transistor, which includes graphene and 2D semiconductor contacting the graphene, and a capacitor connected to the transistor. The memory device may include a first electrode, a first insulation layer, a second electrode, a semiconductor layer, a third electrode, a second insulation layer, and a fourth electrode which are sequentially arranged. The second electrode may include the graphene, and the semiconductor layer may include the 2D semiconductor. Alternatively, the memory device may include first and second electrode elements, a graphene layer between the first and second electrode elements, a 2D semiconductor layer between the graphene layer and the first electrode element, and a dielectric layer between the graphene layer and the second electrode.

Memory devices including two-dimensional material, methods of manufacturing the same, and methods of operating the same

A graphene device including separated junction contacts and a method of manufacturing the same are disclosed. The graphene device is a field effect transistor (FET) in which graphene is used as a channel. A source electrode and a drain electrode do not directly contact the graphene channel, and junction contacts formed by doping semiconductor are separately disposed between the graphene channel and the source electrode and between the graphene channel and the drain electrode. Therefore, in an off state where a voltage is not applied to a gate electrode, due to a barrier between the graphene channel and the junction contacts, carriers may not move. As a result, the graphene device may have low current in the off state.

Graphene device including separated junction contacts and method of manufacturing the same

According to example embodiments, an electronic device includes: a semiconductor layer; a graphene directly contacting a desired (and/or alternatively predetermined) area of the semiconductor layer; and a metal layer on the graphene. The desired (and/or alternatively predetermined) area of the semiconductor layer include one of: a constant doping density, a doping density that is equal to or less than 10cm, and a depletion width of less than or equal to 3 nm.

Electronic device including graphene

A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

Graphene devices and methods of fabricating the same

A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element.

Memory devices including graphene switching devices

A switching device includes a semiconductor layer, a graphene layer, a gate insulation layer, and a gate formed in a three-dimensional stacking structure between a first electrode and a second electrode formed on a substrate.

Three-dimensional graphene switching device

A method of transferring graphene includes patterning an upper surface of a substrate to form at least one trench therein, providing a graphene layer on the substrate, the graphene layer including an adhesive liquid thereon, pressing the graphene layer with respect to the substrate, and removing the adhesive liquid by drying the substrate.

Method of transferring graphene using trench and substrate for receiving graphene

According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Field effect transistor using graphene

Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.

Inverter logic devices including graphene field effect transistor having tunable barrier

An inverter device including a tunable diode device and a diode device that includes a control terminal connected to an input terminal of the inverter device, an anode terminal connected to a high-level voltage terminal, and a cathode terminal connected to an output terminal of the inverter device, wherein the diode device is configured to turn on or off according to a voltage applied to the control terminal.

Inverter device, NAND device, NOR device, and logic device including the same

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Seoul, South Korea

Seong-jun Park