Skhynix Inc.

Seong Ju Lee

Ju Hyuck Kim

Yun Tack Han

Byung Deuk Jeon

Kyu Tae Park

Joon Hong Park

Young Mok Jeong

An artificial intelligence (AI) accelerator includes memory circuits configured to output weight data and vector data, a multiplication circuit/adder tree performing a multiplying/adding calculation on the weight data and the vector data to generate multiplication/addition result data, a first accumulator synchronized with an odd clock signal to perform an accumulative adding calculation on odd-numbered multiplication/addition result data of the multiplication/addition result data and a first latched data, and a second accumulator synchronized with an even clock signal to perform an accumulative adding calculation on even-numbered multiplication/addition result data of the multiplication/addition result data and a second latched data.

Artificial intelligence accelerators

A memory device includes a first comparison circuit suitable for comparing read data read from a plurality of memory cells with write data written in the memory cells and outputting a comparison result, a path selection circuit suitable for transferring selected data selected among the read data and test data as read path data based on the comparison result of the first comparison circuit, and an output data alignment circuit suitable for converting the read path data into serial data to output the serial data as output data.

Memory device and test operation thereof

A memory device includes a data pad disposed in a first pad area and configured to receive data, a data strobe pad disposed in the first pad area and configured to receive a data strobe signal, a clock pad disposed in a second pad area adjacent to the first pad area and configured to receive a clock signal, a data conversion circuit disposed in the first pad area and configured to convert the data inputted through the data pad into parallel data based on the data strobe signal, and a data driving circuit disposed in the first pad area and configured to transmit the parallel data through a global input and output line based on the clock signal.

Semiconductor device including input/output pad

A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in first and second modes. The semiconductor device also includes a data processing circuit configured to latch first to fourth internal data according to first to fourth input control signals. The data processing circuit is additionally configured to generate first to fourth output data by determining the output priority of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, first to fourth rising output control signals, and first to fourth falling output control signals.

Semiconductor device

A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

Memory systems having a plurality of memory devices and methods of training the memory systems

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.

Test modes for a semiconductor memory device with stacked memory chips using a chip identification

A semiconductor device includes a plurality of chips, at least one line, and a controller. Each of the chips includes a chip input/output (I/O) pad, a transceiver configured to perform a transmission operation in response to a transmission enable signal or perform a reception operation in response to a reception enable signal, and a switch configured to couple the chip input/output (I/O) pad to the transceiver in response to a switch enable signal. The at least one line is configured to couple the chip input/output (I/O) pads contained in the plurality of chips. The controller generates the transmission enable signal, the reception enable signal, and the switch enable signal in response to a command signal and a chip identifier (ID) signal.

A test path compensating circuit may include a plurality of electrical paths electrically coupling a plurality of test pads to a test target circuit. The test path compensating circuit may include a control voltage generation circuit configured to generate a plurality of control voltages. The test path compensating circuit may include a plurality of voltage-control delay circuits electrically coupled to the plurality of electrical paths, respectively, and configured to control delay amounts of input test signals received from one or more of the plurality of test pads, based on one or more of the plurality of control voltages, and provide output test signals to the test target circuit.

Growing community of inventors

Hwaseong-si, South Korea

Seong Ju Lee