Sungkyunkwan University

Samsung Electro-mechanics Co., Ltd.

University of Seoul Industry Cooperation Foundation

Silicon Mitus, Inc.

Seong Jin Oh

Kang Yoon Lee

Young Jun Park

Jung Yeon Kim

Hyung Gu Park

Sang Yun Kim

Jong Woo Lee

Je Hyuk Ryu

Hong Jin Kim

Byung Joo Hong

Joong Ho Choi

Keum Cheol Hwang

Youngoo Yang

Ju Hyun Park

Byeong Gi Jang

Dong Soo Lee

In Seong Kim

Han Suk Seo

Ho Jun Shin

Ii Kwon Jang

Kwang Muk Choi

A method of charging a battery by a charging system comprising a master charging circuit and N (N is a natural number) slave charging circuits. The method includes: sourcing a first current to a single-wired bus by the master charging circuit; absorbing (sinking) a second current from the single-wired bus by the N slave charging circuits connected to the single-wired bus; identifying a single-wired bus voltage formed on the single-wired bus at a particular time point by the master charging circuit; and identifying the number of slave charging circuits based on the single-wired bus voltage by the master charging circuit.

Multi-configurable switch mode charging system, charging circuit, and charging method

A clock and data recovery circuit is disclosed herein. The clock and data recovery circuit includes a phase detection unit, a charge pump, a loop filter, a voltage control oscillator, and a frequency detection unit. The voltage control oscillator has oscillation frequency that is variable in response to a frequency adjustment signal, and outputs an oscillation signal. The frequency detection unit includes a reference clock divider, a counter, and an oscillation frequency control unit. The reference clock divider generates a count-enable signal based on a reference clock signal. The counter generates an oscillation count signal by counting the pulses of the oscillation signal of the voltage control oscillator or the pulses of divided signals resulting from dividing the oscillation signal while the count-enable signal is being enabled. The oscillation frequency control unit compares a target count value with the value of the oscillation count signal, and outputs the frequency adjustment signal.

Clock and data recovery circuit using digital frequency detection

Disclosed herein is an active rectifier. The rectifier includes a rectifier unit, a driver unit, and a switching device control circuit unit. The rectifier unit includes first and fourth transistors configured to become conductive when the voltage of an alternating current (AC) input is negative and apply the current of the AC input to a rectifier capacitor, and second and third transistors configured to become conductive when the voltage of the AC input is positive and apply the current of the AC input to the rectifier capacitor. The driver unit outputs first to fourth drive control signals, and drives the first to fourth transistors. The switching device control circuit unit compares the first drive control signal and the second drive control signal with the AC input, and outputs switching device control signals to delay the first to fourth drive control signals based on the extents to delay.

Active rectifier capable of preventing reverse leakage current

A rectifier includes: a rectifying circuit configured to rectify alternating current (AC) power into direct current (DC) power through a switching operation; a driver configured to apply a switching signal to the rectifying circuit; and a signal modulator configured to select a parameter from among parameters of the switching signal based on a frequency of the switching signal, and adjust the selected parameter.

Rectifier and method of controlling the same

Growing community of inventors

Suwon-si, South Korea

Seong Jin Oh