Samsung Electronics Co., Ltd.

Seong-Jin Lee

Ju-yun Jung

Yoo-Jung Lee

Jang Seok Choi

A memory device including; a memory cell array including memory cells connected to word lines and bit lines, and redundancy memory cells connected to a redundancy word line and the bit lines, and control logic configured to control execution of a post package repair operation by the memory device. The control logic includes a PPR control circuit that programs a bad row address to a non-volatile memory during a normal PPR operation in response to the normal PPR command, and programs the bad row address to a volatile memory during a fast PPR operation in response to the fast PPR command, and replaces the bad row in the memory cell array with a redundancy row associated with the redundancy word line.

Memory device performing post package repair (PPR) operation

The semiconductor device is provided. The semiconductor device includes a substrate, an electrostatic discharge layer disposed on the substrate and including a plurality of electrostatic discharge circuits, at least one semiconductor chip stacked on the electrostatic discharge layer, and a plurality of vertical electrical connections which pass through the at least one semiconductor chip and the electrostatic discharge layer to connect the at least one semiconductor chip to the semiconductor substrate. The vertical electrical connections are connected to the electrostatic discharge circuits, respectively.

Growing community of inventors

Hwaseong-si, South Korea

Seong-Jin Lee