Samsung Electronics Co., Ltd.

Other

Seong-Jin Jang

Kwang-il Park

Seung-Jun Bae

Ho-Young Song

Jong-Pil Son

Woo-Jin Lee

Joung-Yeal Kim

Byung-sik Moon

Young-Hyun Jun

Sang-woong Shin

Jin-seok Kwak

Sang-Uhn Cha

Hoi-ju Chung

Ho-young Song

Jong-Min Oh

Ju-Seop Park

Hyun-Jin Kim

Min-Sang Park

Kyoung-Ho Kim

Jeong-Don Lim

Beom-Sig Cho

Jin-Seok Kwak

Sung-Hoon Kim

Hyun-jin Kim

Jung-Hwan Choi

Jin-ho Kim

Seok-Hun Hyun

Young-Yong Byun

Ki-Heung Kim

Tae-Yoon Lee

Kwang-II Park

Jeong-Kyoum Kim

Chul-woo Park

Jung-bae Lee

Nam-seog Kim

Uk-Song Kang

Reum Oh

Hyeoung-won Seo

Sang-Joon Hwang

Hoon Bok Lee

Soo-Ho Shin

Jun-Bae Kim

Yong-Ho Cho

Doo-young Kim

Dong-hyeon Jang

Won-woo Lee

Ji-Hoon Lim

Sang-Yun Kim

Jeong-soo Park

Youn-sik Park

Young-Uk Chang

Woo-Dong Lee

Chul-woo Yi

Tai-Young Ko

Sang-kyun Park

Sin-Ho Kim

Sam-Young Bang

Sang-Seok Kang

Kyu-Hyoun Kim

Tae-Young Oh

Hyoung-Joo Kim

Jun-hyung Kim

Sang-Bo Lee

Young-chul Cho

Kyu-Nam Lim

Jong-Ho Moon

Su-Jin Park

Hye-Ran Kim

Sung-Min Seo

Je-Min Ryu

Ye-Sin Ryu

Myeong-O Kim

Won-Il Bae

Chul-Soo Kim

Dong-Hak Shin

In-Dal Song

Soo-Hwan Kim

Hyun-chul Yoon

Hyuck-Chai Jung

Gil-Su Kim

Hong-Jun Lee

Cheon-An Lee

Yu-Lim Lee

Hyun-Dong Kim

Chang-Man Khang

Seung-Hoon Oh

Hyuk-joon Kwon

Seung-jun Bae

Ho-Kyong Lee

Won-hwa Shin

Ho-Yong Song

A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

Semiconductor memory devices and memory systems including the same

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Semiconductor memory devices, memory systems including the same and methods of operating the same

A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

Memory device having error notification function

A memory device that operates in a low-power operation mode includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the number of data items prefetched in the memory cell array according to a power mode during a read operation. The encoding and decoding changing circuit changes a level of data written in the memory cell array according to the power mode during a read operation.

Memory device having different data-size access modes for different power modes

A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

Semiconductor device capable of rescuing defective characteristics occurring after packaging

A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

Data loading circuit and semiconductor memory device comprising same

A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Fuse data reading circuit having multiple reading modes and related devices, systems and methods

An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Optical transmission converter, memory system comprising same, and related method of operation

A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.

3D semiconductor device

An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.

Anti-fuse circuit in which anti-fuse cell data is monitored, and semiconductor device including the same

A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Memory device from which dummy edge memory block is removed

Growing community of inventors

Seongnam-si, South Korea

Seong-Jin Jang