Electronics and Telecommunications Research Institute

Seong Il Kim

Ho Kyun Ahn

Jong Won Lim

Sang Heung Lee

Hae Cheon Kim

Hyung Sup Yoon

Dong Min Kang

Jong Min Lee

Hyun Wook Jung

Byoung Gue Min

Chull Won Ju

Youn Sub Noh

Kyung Ho Lee

Sung Jae Chang

Eun Soo Nam

Kyu Jun Cho

Il Gyu Choi

Soo Cheol Kang

Jong-Won Lim

Byoung-Gue Min

Sang-Heung Lee

Yong-Hwan Kwon

Dong-Young Kim

Yong Hwan Kwon

Zin Sig Kim

Jae Won Do

Chul Won Ju

Young Il Kang

An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.

Electrical circuit of semiconductor channel resistor and apparatus and method for generating the same

A method of manufacturing a high-electron-mobility transistor device is provided. The method includes sequentially forming a transition layer and a semiconductor layer on a substrate, etching a portion of a surface of the semiconductor layer to form a barrier layer region having a certain depth and forming a barrier layer in the barrier layer region, forming a source electrode and a drain electrode on a 2-dimensional electron gas (2-DEG) layer upward exposed at a surface of the semiconductor layer, in defining the 2-DEG layer formed along an interface between the semiconductor layer and the barrier layer, forming a passivation layer on the semiconductor layer, the barrier layer, the source electrode, and the drain electrode and etching a portion of the passivation layer to upward expose the source electrode, the drain electrode, and the barrier layer, and forming a gate electrode on the upward exposed barrier layer.

High-electron-mobility transistor device and method of manufacturing the same

The present invention improves a heat dissipation property of a semiconductor device by transferring hexagonal boron nitride (hBN) with a two-dimensional nanostructure to the semiconductor device. A semiconductor device of the present invention includes a substrate having a first surface and a second surface, a semiconductor layer formed on the first surface of the substrate, an hBN layer formed on at least one surface of the first surface and the second surface of the substrate, and a heat sink positioned on the second surface of the substrate. A radiation rate of heat generated during driving of an element is increased to decrease a reduction in lifetime of a semiconductor device due to a temperature increase. The semiconductor device has a structure and configuration which are very effective in improving a rapid temperature increase due to heat generated by high-power semiconductor devices.

Semiconductor device with high heat dissipation property using hexagonal boron nitride and method of manufacturing the same

A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.

High electron mobility transistor and fabrication method thereof

Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.

Semiconductor device and fabrication method thereof

Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.

Feedback amplifier

Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.

Component package including matching circuit and matching method thereof

Disclosed are a semiconductor device having a stable gate structure, and a manufacturing method thereof, in which a gate structure is stabilized by additionally including a plurality of gate feet under a gate head in a width direction of the gate head so as to serve as supporters in a gate structure including a fine gate foot having a length of 0.2 &#x3bc;m or smaller, and the gate head having a predetermined size. Accordingly, it is possible to prevent the gate electrode of the semiconductor device from collapsing, and improve reliability of the semiconductor device during or after the process of the semiconductor device.

Semiconductor device having stable gate structure and method of manufacturing the same

Provided are a chip, a chip stack, and a method of manufacturing the same. A plurality of chips which each include: at least one pad formed on a wafer; and a metal layer which protrudes up to a predetermined thickness from the bottom of the wafer and is formed in a via hole exposing the bottom of the pad are stacked such that the pad and the metal layer of adjacent chips are bonded. This leads to a simplified manufacturing process, high chip performance and a small footprint for a chip stack.

Method of manufacturing a chip

Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter to expose the base layer by sequentially etching the emitter capping layer and the emitter layer using the emitter electrode as an etch mask in vertical and negative-sloped directions to the substrate, respectively; and forming a base electrode on the exposed base layer using the emitter electrode as a mask in self-alignment with the emitter electrode. In this method, a distance between the mesa type emitter and the base electrode can be minimized and reproducibly controlled. Also, a self-aligned device with an excellent high-frequency characteristic can be embodied.

Growing community of inventors

Daejeon, South Korea

Seong Il Kim