Hynix Semiconductor Inc.

Seong Hun Park

Jong Hyun Wang

Duck Ju Kim

Chae Kyu Jang

Chang Won Yang

Se Chun Park

Joong Seob Yang

Suk Yun

A non-volatile memory device comprises a voltage supplier comprising memory cells in which the voltage supplier supplies a positive set voltage to a bulk of a memory cell array at the time of a read operation of the memory cells and a controller for controlling the voltage supplier to set and supply a bulk voltage depending on a number of erase/program cycles of the memory cell array.

Non-volatile memory device and method of controlling a bulk voltage thereof

A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.

Memory device and method of operating the same

A flash memory device includes a memory cell array including a plurality of memory cells, a page buffer unit including a plurality of page buffers connected to bit lines of the memory cell array, a data line mux unit connected between the page buffer unit and a data line and configured to receive verification data through a page buffer during a verify operation. The flash memory device also includes a fail bit counter unit for counting the verification data, comparing counted fail bits and the number of ECC allowed bits, and outputting a pass or fail signal of a program operation according to the comparison result.

Flash memory device and programming method thereof

Program voltages of a non-volatile memory device are controlled variably according to a program/erase operation count. The non-volatile memory device includes a program voltage supply unit for applying a program voltage to a memory cell, a program/erase count storage unit for storing a total program/erase operation count of the non-volatile memory device, a program start voltage storage unit for storing levels of program start voltages to be differently supplied according to the program/erase operation count, and a program voltage controller for controlling the program start voltage according to the program/erase operation count.

Non-volatile memory device and method of operating the same

A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. The first register is connected to the even bit line and configured to store specific data. The second register is connected to the odd bit line and configured to store specific data. The first precharge unit precharges an even sense node, formed at a node of the even bit line and the first register, with a high level or supplies supplementary current to the even sense node. The second precharge unit precharges an odd sense node, formed at a node of the odd bit line and the second register, with a high level or supplies supplementary current to the odd sense node. The bit line select unit connects the even bit line and the even sense node and connects the odd bit line and the odd sense node.

Non-volatile memory device and data read method and program verify method of non-volatile memory device

A non-volatile memory device of the present invention includes a page buffer having a bit line selecting circuit, a first register, a second register, a data comparing circuit, a first bit line voltage controller, and a second bit line voltage controller. The bit line selecting circuit couples selectively a certain bit line to a sensing node. The first register and the second register store given data. The data comparing circuit compares the data stored in the first register with the data stored in the second register, and transmits the comparison result to the sensing node. The first bit line voltage controller applies a voltage of low level to the bit line in accordance with a voltage level of the data stored in the first register. The second bit line voltage controller applies a selected first voltage of high level to the bit line in accordance with the data stored in the second register.

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Gunsan-si, South Korea

Seong Hun Park