Samsung Electronics Co., Ltd.

Phicom Corporation

Seoul National University

Seong-Hoon Jeong

Yu-Gyun Shin

Dong-Chan Kim

Jong-Ryeol Yoo

Tai-Su Park

Jong-Hoon Kang

Jeong-Do Ryu

Si-Young Choi

Sung-Min Kim

Cheol Kyu Kim

Soo-Jung Ryu

Ho-Young Kim

Heon-jong Shin

Young-chul Cho

Kong-Soo Lee

Jae-Jong Han

Hyun-jung Lee

Soo-jin Hong

Deok-hyung Lee

Jin-Sae Jung

Kyung-Seok Oh

Yoon-Goo Kang

Woo-seok Hwang

Han-jin Lim

Jeong-yeon Lee

Bernhard Egger

Heui-jin Kwon

Dong-Kyu Lee

Oug-Ki Lee

Moo-Kyoung Chung

Hee-jun Shim

Won-Seok Yoo

Yen-Jo Han

Ho-Kyun An

Jung-Sup Oh

Jung-Soo An

Gun-Joong Lee

Changyeon Jo

Jung-Geun Park

Kyu-Hyun Shin

Jung-Sun Yoo

Daeyong Shin

A simulation apparatus and a distribution simulation system are disclosed. The simulation apparatus, according to one example, includes a simulation executer configured to execute a simulation task, a data storage configured to store data related to the simulation task based on a data storage policy that is set in advance of the execution of the simulation tasks, and a data updater configured to update the data stored in the data storage to most recent data by comparing the data stored in the data storage with data stored in another simulation apparatus.

Simulation device and distribution simulation system

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a lower fin that protrudes from a substrate and extends in a first direction, an oxide film the lower fin, an upper fin that protrudes from the oxide film and that is spaced apart from the lower fin at a position corresponding to the lower fin, and a gate structure the upper fin that extends in a second direction to intersect the upper fin, wherein germanium (Ge) is included in a portion of the oxide film located between the lower fin and the upper fin.

Semiconductor devices having lower and upper fins and method for fabricating the same

A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Method and apparatus for generating test bench for verification of processor decoder

An apparatus for generating a test case includes a constrained description generator configured to define a plurality of constrained verification spaces in a total verification space, and generate a constrained description for each of the plurality of constrained verification spaces; and a test case generator configured to generate a test case using the constrained description.

Apparatus and method for generating test cases for processor verification, and verification device

A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection. A first blocking layer is provided between the lower interconnection and the switching device. The first blocking layer includes carbon (C), germanium (Ge), or a combination thereof. A second blocking layer may be provided between the substrate and the lower interconnection.

Semiconductor devices having blocking layers and methods of forming the same

A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor

A method for verifying an operation of a reconfigurable processor is provided. The method includes generating a random test program using a test description and an architecture description, executing the generated random test program in the reconfigurable processor and in a simulator, and then comparing types of output values in the execution result.

Method for verification of reconfigurable processor

Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

Semiconductor devices having a vertical diode and methods of manufacturing the same

In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices

Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls

In semiconductor devices, methods of forming the same, the semiconductor device include a first gate structure having a first gate oxide layer pattern, a first polysilicon layer pattern containing atoms larger than silicon and a first hard mask layer pattern on substrates under tensile stress. N-type impurity regions are formed under the surface of the substrate on both sides of the first gate structure. A second gate structure having a second gate oxide layer pattern, a second polysilicon layer pattern containing atoms smaller than silicon and a second hard mask layer pattern on substrates under compressive stress. Additionally, P-type impurity regions are formed under the surface of the substrate on both sides of the second gate structure. The semiconductor devices have good device properties.

Semiconductor devices having polysilicon gate layer patterns and methods of manufacturing the same

Digital television with a graphical user interface

Growing community of inventors

Masan-si, South Korea

Seong-Hoon Jeong