Samsung Electronics Co., Ltd.

Seong-Ho Moon

Dong-Woo Kim

Hong-Sik Yoon

Sun-Woo Lee

So-Ra Han

Seung-Hune Yang

Artem Shamsuarov

Bo-un Yoon

Hyo-San Lee

Jung-Hyeon Kim

Yool Kang

Kun-Tack Lee

Seong-woon Choi

Moon-Gyu Jeong

Seok-Hwan Oh

Dae-Hyuk Kang

Subramanya Mayya

Seong-Bo Shim

Hyoung-hee Kim

Xiaofeng Wang

Dmitry Vengertsev

A block management method for OPC model calibration includes calculating differences in several different optical functions between first patterns of a first mask and patterns of a second mask corresponding to the first patterns but differing therefrom by a predetermined bias, selecting one or more of the optical functions based on the calculated differences, clustering data of variations in the values of the calculated differences in the selected ones of the optical functions, selecting respective ones of the first patterns in consideration of how the data clusters, and designating the selected first patterns as test patterns.

Test pattern selection method for OPC model calibration

Provided is a method of manufacturing a photo-mask having a micro pattern. The method includes providing an analyzing design layout, dividing the analyzing design layout into a two-dimensionally repeated portion, a one-dimensionally repeated portion, and a non-repeated portion, forming a first corrected layout by performing optical proximity correction (OPC) in the two-dimensionally repeated portion, forming a second corrected layout, taking account of the first corrected layout, by performing OPC in the one-dimensionally repeated portion, forming a third corrected layout, taking account of the first corrected layout and the second corrected layout, by performing OPC in the non-repeated portion, and forming a photo-mask based on the first through third corrected layouts.

Method of manufacturing photo-mask

A method of forming a mask pattern, a method of forming a minute pattern, and a method of manufacturing a semiconductor device using the same, the method of forming the mask pattern including forming first mask patterns on a substrate; forming first preliminary capping layers on the first mask patterns; irradiating energy to the first preliminary capping patterns to form second preliminary capping layers ionically bonded with the first mask patterns; applying an acid to the second preliminary capping layers to form capping layers; forming a second mask layer between the capping layers, the second mask layer having a solubility lower than that of the capping layers; and removing the capping layers to form second mask patterns.

Method of forming a mask pattern, method of forming a minute pattern, and method of manufacturing a semiconductor device using the same

In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole

In a memory device having a carbon nanotube and a method of manufacturing the same, the memory device includes a lower electrode, an upper electrode having a first void exposing a sidewall of a diode therein, an insulating interlayer pattern having a second void exposing a portion of the lower electrode between the lower electrode and the upper electrode, and a carbon nanotube wiring capable of being electrically connected with the diode of the upper electrode by a voltage applied to the lower electrode. The memory device may reduce generation of a leakage current in a cross-bar memory.

Memory devices having a carbon nanotube

In a method of forming a wiring having a carbon nanotube, a lower wiring is formed on a substrate, and a catalyst layer is formed on the lower wiring. An insulating interlayer is formed on the substrate to cover the catalyst layer, and an opening is formed through the insulating interlayer to expose an upper face of the catalyst layer. A carbon nanotube wiring is formed in the opening, and an upper wiring is formed on the carbon nanotube wiring and the insulating interlayer to be electrically connected to the carbon nanotube wiring. A thermal stress is generated between the carbon nanotube wiring and the upper wiring to produce a dielectric breakdown of a native oxide layer formed on a surface of the carbon nanotube wiring. A wiring having a reduced electrical resistance between the carbon nanotube wiring and the upper wiring may be obtained.

Method of forming a wiring having carbon nanotube

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Yongin-si, South Korea

Seong-Ho Moon