Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Seong-Ho Lee

Jun Cao

Afshin Momtaz

Kenneth C Ma

Stephen Petilli

Michael Q Le

Ali Nazemi

Hui Pan

Christopher Pasqualino

Anand Jitendra Vasani

Burak Catli

Wei Zhang

Kun Chuai

Hyung-Joon Jeon

Hao O Phung

Angus Tang

Sakyun Hwang

SangHye Chung

Vadim Milirud

An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine integral non-linearity of the phase interpolator at the first code based on the total delay. The control logic may further calibrate a first code of a phase interpolator based, at least in part, on the integral non-linearity.

INL detection and calibration for phase-interpolator

A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.

Pre-driver peaking technique for high-speed DACs

Inter-chip connectivity may be provided in a computing device, which may comprise a USB host and at and at least one USB device embedded within the computing device, based on Universal Serial Bus version 3.0 (USB3.0) interface. In this regard, internal communication of data between the USB host and embedded USB device may be performed via USB3.0 SuperSpeed signals. The USB host and/or the USB3.0 interface may be configured to enable USB3.0 internal communication of data, and to reduce power consumption during the internal communication of data compared to external USB3.0 communications. Configuration of the USB3.0 interface for internal communication of data may comprises modifying and/or adjusting physical (PHY) layer, link layer, and/or protocol layer related parameters, functions, resources, and/or operations. The USB3.0 SuperSpeed signals may be communication using scalable low voltage signaling (SLVS). In this regard, Input/Output (IO) Swing may be set based on loopback training sequence.

Method and system for utilizing low power superspeed inter-chip (LP-SSIC) communications

A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

System for shifting data bits multiple times per clock cycle

A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.

System and method for recovering and deserializing a high data rate bit stream

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Aliso Viejo, CA, United States of America

Seong-Ho Lee