Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Seong-Ho Kim

Dong-Gun Park

Jeong-Dong Choe

Chang-Sub Lee

Shin-Ae Lee

Sung-min Kim

Sung-Min Kim

Gil-Sub Kim

Won-mo Park

Dong-Kwan Yang

Dong-Won Lee

Young-Il Kim

Seong-Hyun Jin

Ho-Ju Song

Sung-Ho Choi

Jong-Min Lee

Sung-Jin Kim

Sang-Hun Park

Young-Mok Son

Tae-Yong Noh

Jung-su Han

Won-Jin Kim

Hyea-Weon Shin

Hae-jeong Lee

Hae-Chul Lee

Se-Wook Oh

Sung-won Park

Ju-Wan Han

Seung-yup Lee

Joong-Ki Kwon

Woo-Jae Kwon

Yong-Suk Shin

Tae-Yong Hong

Uk-hyeon Shin

Sang-un Oh

An organic light emitting display apparatus includes a substrate; a thin film transistor which is disposed over the substrate; a first electrode which is disposed over the substrate and electrically connected to the thin film transistor; a passivation layer which covers the thin film transistor and contacts a predetermined region of an upper surface of the first electrode; an intermediate layer which is disposed over the first electrode, includes an organic emission layer, and contacts a predetermined region of the passivation layer; and a second electrode which is disposed over the intermediate layer.

Organic light emitting display apparatus and method of manufacturing the organic light emitting display apparatus

A method of manufacturing a radar transparent cover may include steps of: injection molding a first transparent cover; inserting into a mold the first transparent cover made by the step of injection molding the first transparent cover and then, double injection molding a color resin on a back surface of the first transparent cover; and inserting into a mold the injection molded article made by the step of double injection molding the color resin and then, double injection molding a second transparent cover on a front surface of the first transparent cover.

Method of manufacturing radar transparent cover for vehicles and radar transparent cover manufactured thereby

A method performed by at least one processor of a wireless communication apparatus including a plurality of internal components, the method includes generating a plurality of sets of noise information corresponding to a plurality of test noise signals generated by the plurality of internal components under a plurality of state conditions, receiving a radio frequency (RF) signal, determining a magnitude of a noise signal that interferes with the RF signal by using a set of noise information corresponding to a current state condition from among the plurality of sets of noise information, and performing noise filtering on the RF signal based on a magnitude of the RF signal and the magnitude of the noise signal.

Wireless communication apparatuses performing selective noise filtering and methods of operating the same

An organic light-emitting display device preventing edge defects between a pixel define layer and a pixel electrode, and a method of manufacturing the same. The organic light-emitting display device, comprises: a substrate; a pixel electrode disposed on the substrate and comprising a first patterned unit and a second patterned unit which are electrically disconnected; a pixel define unit disposed on the substrate and exposing the pixel electrode; an intermediate layer disposed on the pixel electrode and emitting light; and a counter electrode disposed on the intermediate layer and the pixel define layer.

Organic light-emitting display device preventing edge defects between pixel define layer and pixel electrode, and method of manufacturing the same

A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.

Fuse structures, e-fuses comprising fuse structures, and semiconductor devices comprising e-fuses

A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.

Semiconductor device including fuse having form of capacitor

A printing method and a printer for implementing the printing method are disclosed. When a printhead including a first end and a second end sequentially prints a first area and a second area which are adjacent to each other, the method comprises performing printing by means of the printer by relatively moving locations of the printhead and a print object in such a way that a surface printed by the second end in the first area and a surface printed by the second end in the second area face each other. The printhead rotates around a rotational axis comprising at least one point on the printhead, one end of the printhead, a center of the printhead, or both ends of the printhead.

Printing method and printer

A structure included in a semiconductor device can include a fuse box guard ring that defines an interior region of the fuse box inside the fuse box guard ring and that defines an exterior region of the fuse box outside the fuse box guard ring. The fuse box guard ring can include protruding support members that protruding from an interior sidewall or from an exterior sidewall of the fuse box guard ring.

Fuse box guard rings including protrusions and methods of forming same

Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.

Semiconductor memory device including a cylinder type storage node and a method of fabricating the same

A method of forming a semiconductor memory device includes sequentially forming an etch stop layer and then a mold layer, forming a plurality of line-shaped support structures and a first sacrificial layer filling gaps between the support structures on the mold layer, sequentially forming a plurality of line-shaped first mask patterns, a second sacrificial layer, and then second mask patterns on the support structures and on the first sacrificial layer, removing the second sacrificial layer, the first sacrificial layer, and the mold layer using the first mask patterns, the second mask patterns, and the support structures as masks, removing the first mask patterns and second mask patterns, filling the storage node electrode holes with a conductive material and etching back the conductive material to expose the support structures, and removing the first sacrificial layer and the mold layer to form pillar-type storage node electrodes supported by the support structures.

Method of forming capacitor of semiconductor memory device

A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Methods of fabricating semiconductor devices with enlarged recessed gate electrodes

Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Methods of fabricating field effect transistors having multiple stacked channels

Semiconductor devices with enlarged recessed gate electrodes

MOS transistors have an active region defined in a portion of a semiconductor substrate, a gate electrode on the active region, and drain and source regions in the substrate. First and second lateral protrusions extend from the lower portions of respective sidewalls of the gate electrode. The drain region has a first lightly-doped drain region under the first lateral protrusion, a second lightly-doped drain region adjacent the first lightly-doped drain region, and a heavily-doped drain region adjacent to the second lightly-doped drain region. The source region similarly has a first lightly-doped source region under the second lateral protrusion, a second lightly-doped source region adjacent the first lightly-doped source region, and a heavily-doped source region adjacent to the second lightly-doped source region. The second lightly-doped regions are deeper than the first lightly-doped regions, and the gate electrode may have an inverted T-shape.

MOS Transistors having inverted T-shaped gate electrodes and fabrication methods thereof

Growing community of inventors

Gyeonggi-do, South Korea

Seong-Ho Kim