Samsung Electronics Co., Ltd.

Applied Precision, Inc.

Seong-ho Cho

Myoung-jae Lee

Moon-seung Yang

Mohammad Rakib Uddin

Sung-Hun Lee

David Seo

Sang-moon Lee

Dong-Soo Lee

Dong-ho Lee

Ji-hyun Hur

Hee-jeong Jeong

Eui-chul Hwang

In-kyeong Yoo

Ho-jung Kim

Jeo-young Shim

Chang-rok Moon

Duck-hyung Lee

Tae-han Jeon

Young-soo Park

Hyun-jong Chung

Dong-Shin Jung

Ho-Yeon Park

Su-hyeon Kim

Won-Seok Kwon

Carl S Brown

Kun-sun Eom

Hyoung-Shick Kim

June-young Lee

Kyu-Sang Lee

Kyla Teplitz

According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.

Graphene device and method of manufacturing the same

The present disclosure relates to a semiconductor device including an oxygen gettering layer between a group III-V compound semiconductor layer and a dielectric layer, and a method of fabricating the semiconductor device. The semiconductor device may include a compound semiconductor layer; a dielectric layer disposed on the compound semiconductor layer; and an oxygen gettering layer interposed between the compound semiconductor layer and the dielectric layer. The oxygen gettering layer includes a material having a higher oxygen affinity than a material of the compound semiconductor layer.

Semiconductor device and method of fabricating the same

A substrate structure, a complementary metal oxide semiconductor (CMOS) device including the substrate structure, and a method of manufacturing the CMOS device are disclosed, where the substrate structure includes: a substrate, at least one seed layer on the substrate formed of a material including boron (B) and/or phosphorus (P), and a buffer layer on the seed layer. This substrate structure makes it possible to reduce the thickness of the buffer layer and also improve the performance characteristics of a semiconductor device formed with the substrate structure.

Substrate structure, complementary metal oxide semiconductor device, and method of manufacturing complementary metal oxide semiconductor device

A nanosensor may include a substrate that has a hole formed therein, a first insulating layer that is disposed on the substrate and has a nanopore formed therein, first and second electrodes that are disposed on the first insulating layer and are spaced apart from each other, first and second electrode pads that are disposed on the first and second electrodes, respectively, and a protective layer disposed on the first and second electrode pads. A method of manufacturing a nanosensor may include forming a first insulating layer, graphene, and a metal layer on a substrate, patterning the metal layer and the graphene, forming a protective layer on a portion of the graphene and the metal layer, exposing a portion of the graphene by removing a portion of the protective layer, forming a hole in the substrate, and forming a nanopore in the first insulating layer and the graphene to be connected to the hole.

Nanosensor and method of manufacturing same

Provided are a complementary metal oxide semiconductor (CMOS) device and a method of manufacturing the same. In the CMOS device, a buffer layer is disposed on a silicon substrate, and a first layer including a group III-V material is disposed on the buffer layer. A second layer including a group IV material is disposed on the buffer layer or the silicon substrate while being spaced apart from the first layer.

Complementary metal oxide semiconductor device and method of manufacturing the same

Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic.

Nonvolatile memory transistor and device including the same

An athermal optical modulator includes a waveguide, a ring resonator configured to receive light input from the waveguide and output modulated light to the waveguide, the ring resonator including a ridge unit located at a center of the ring resonator in a vertical section, a first contact connected to one side of the ridge unit and a second contact connected to the other side of the ridge unit, the first contact and the second contact forming paths for applying electricity to the ring resonator to form an electric field in the ring resonator, and a polymer layer covering the ridge unit.

Athermal optical modulator and method of manufacturing the same

An optoelectronic chip, and/or a method of manufacturing the same, include a substrate; a coupler region surrounded by the substrate. The coupler region includes a total reflection surface. The total reflection surface is configured to totally reflect a first light incident through a surface of the substrate such that the reflected first light travels within the substrate, or the total reflection surface is configured to totally reflect a second light guided in the substrate and incident on the total reflecting surface such that the reflected second light travels through the surface of the substrate.

Optoelectronic chips including coupler region and methods of manufacturing the same

A semiconductor device is provided that includes a diffusion barrier layer between a compound semiconductor layer and a dielectric layer, as well as a method of fabricating the semiconductor device, such that the semiconductor device includes a compound semiconductor layer; a dielectric layer; and a diffusion barrier layer including an oxynitride formed between the compound semiconductor layer and the dielectric layer.

A nanogap sensor includes a first layer in which a micropore is formed; a graphene sheet disposed on the first layer and including a nanoelectrode region in which a nanogap is formed, the nanogap aligned with the micropore; a first electrode formed on the grapheme sheet; and a second electrode formed on the graphene sheet, wherein the first electrode and the second electrode are connected to respective ends of the nanoelectrode region.

Nanogap sensor and method of manufacturing the same

An optical modulator includes a first graphene and a second graphene on an upper surface of a semiconductor layer, a first electrode on the first graphene, and a second electrode on the second graphene. Respective side surfaces of the first graphene and the second graphene are separated from each other. A first ridge portion of the semiconductor layer and a second ridge portion on the second graphene constitute an optical waveguide, and the first and second graphenes are on a center portion of the optical waveguide in a vertical direction to the semiconductor.

Optical modulator including graphene

An optoelectronic chip including a coupler region, and a method of manufacturing the same, include a substrate; a coupler region formed of a material having a refractive index lower than the substrate and surrounded by the substrate. The coupler region includes a total reflection surface that totally reflects light incident through a surface of the substrate into the substrate or emits light guided in the substrate through the surface of the substrate.

A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.

Method of fabricating optoelectronic integrated circuit substrate

An integrated bio-chip includes; a sample detection portion including at least one light receiving device which detects fluorescent light emitted from at least one sample, a light transfer portion disposed on a light incident surface of the sample detection portion, and which includes at least one excitation light absorbing waveguide which absorbs an excitation light and transmits the fluorescent light emitted from the at least one sample, and a sample reaction portion disposed adjacent to an incident end of the at least one excitation light absorbing waveguide, and including at least one reaction region on which the at least one sample is attached, wherein the sample detection portion, the light transfer portion, and the sample reaction portion are integrally coupled to each other as a single component.

Growing community of inventors

Gwacheon-si, South Korea

Seong-ho Cho