Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Lg Electronics Inc.

Dongbu Hitek Co., Ltd.

Seong-Gyun Kim

Sung-Woo Park

Ji-hoon Park

Seung-Beom Yoon

Sang-Woo Kang

Sung-Taeg Kang

Yong-suk Choi

Bo-Young Seo

Jeong-Uk Han

Ju-Cheon Yeo

Du-Hwan Oh

Eun-Kyung Hong

Seong-Ho Cho

Su-Hyung Kim

Ho-Min Jeon

Woo-Ram Seong

A luminance controller of an OLED device and the OLED device including the luminance controller include a peaking processor for calculating a minimum gray level value by filtering low gray level data from primary RGB data and determining a compensation gain value corresponding to the minimum gray level value; a boosting processor for calculating a maximum gray level value by filtering high gray level data from the primary RGB data, calculating a gain value corresponding to the maximum gray level value, and calculating a coloring ratio coefficient using the minimum gray level value and the maximum gray level value; and a secondary RGB generator for generating secondary RGB data by applying the compensation gain value, the coloring ratio coefficient, and the gain value to the primary RGB data.

Method and apparatus for controlling luminance of organic light emitting diode display device

Disclosed are an apparatus and method for correcting a depth map for a three-dimensional image, which are capable of accurately correcting an initially-generated depth map in accordance with characteristics of an image, thereby achieving an enhancement in picture quality of a three-dimensional image. The disclosed apparatus includes an original depth map generating unit for generating an original depth map for frame image data externally supplied to the original depth map generating unit, and a depth map correcting unit for analyzing the externally-supplied frame image data, calculating an image pattern of the frame image data and per-pixel brightness values of the frame image data, based on results of the analysis, and correcting the original depth map output from the original depth map generating unit, based on the calculated image pattern and the calculated brightness values, thereby generating a corrected depth map.

Apparatus and method for correcting depth map for three-dimensional image

Disclosed are an organic light emitting diode (OLED) display device and a method for driving the same, which are capable of minimizing required memory capacity and the use rate thereof while achieving an enhancement in display quality through execution of an overdriving (or accelerated driving) in accordance with image information of plural accumulated frames. The OLED display device includes a data modulator for sequentially receiving image data of a current frame from a timing controller, counting a number of accumulations of pixels corresponding to image data having a lower grayscale value than a grayscale value of predetermined reference data, generating modulated image data through application of a weight determined in accordance with the counted accumulation number, and supplying the modulated image data to a data driver.

Organic light emitting diode display and method for driving the same

An apparatus and method for driving an image display apparatus are disclosed. The apparatus includes a display panel having a plurality of pixels, for displaying an image, a panel driver for driving the pixels of the display panel, an image data converter for detecting a smooth region, an edge region, and a detail region from externally input image data in units of at least one frame and generating converted image data by changing a gray scale or chrominance of the image data at different rates in the smooth region, the edge region and the detail region, and a timing controller for arranging the converted image data suitably for driving of the display panel, providing the arranged image data to the panel driver, and controlling the panel driver by generating a panel control signal.

Apparatus and method for driving image display apparatus

A method of driving a display device includes outputting an upper data signal array of a (n+1)frame to an upper display area of a display panel during a first frame period; and, outputting a lower data signal array of a nframe to a lower display area of the display panel during the first frame period is provided. The display panel has at least an upper display area and a lower display area which may be independently operable, the display areas communicating with a memory device storing and outputting a signal data array of a (n+1)frame to an upper display area of a display panel during a first frame period; and, outputting a lower data signal array of a nframe to a lower display area of the display panel during the first frame period.

Organic electroluminescent display device including upper and lower display areas and driving method thereof

An organic electro luminescence device includes first, second, and third switching elements connected in series with each other, the first switching element controlled by a first signal, and the second and third switching elements controlled by a second signal, the second signal being different from the first signal, a first driving element connected to a power source, a storage capacitor, and the first, second and third switching elements, and a second driving element connected to the power source, the storage capacitor, an organic light emitting diode, and the third switching element.

Organic electro luminescence device

A method of driving a liquid crystal display device having a plurality of gate lines, a plurality of data lines and a plurality of pixel electrodes includes: applying sequentially a gate signal to the plurality of gate lines, the gate signal being applied to odd gates lines of the plurality of gate lines for a first pulse time period and being applied to even gate lines of the plurality of gate lines for a second pulse time period shorter than the first pulse time period; and supplying a data signal to each of the plurality of data lines.

Method of driving liquid crystal display device

A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Non-volatile memory devices and methods of forming the same

Embodiments relate to a three-dimensional flash memory cell and method of forming the same that may be improve the uniformity of flash memory cell by removing a width difference of a polysilicon pattern when forming a floating gate of flash memory device, to thereby improve the reliability of semiconductor device. The process may be simplified due to the self-alignment in the step of forming the polysilicon pattern, which may improve the yield.

Three-dimensional flash memory cell

Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

EEPROM device having first and second doped regions that increase an effective channel length

A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

Flash memory device using semiconductor fin and method thereof

An electrically erasable and programmable read only memory (EEPROM) device may include: a gate oxide layer on a semiconductor substrate, the gate oxide layer including a first segment of a first thickness, a second segment of a second thickness, and a tunneling third segment of a third thickness, the second thickness being thicker than the first thickness and the third thickness being thinner than the first thickness; a floating junction region formed under a portion of the gate oxide layer in the semiconductor substrate; and a floating gate, an insulating layer pattern, and a control gate which are sequentially formed, respectively, on the gate oxide layer.

EEPROM device for increasing a coupling ratio and fabrication method thereof

Provided are a local SONOS-type memory device and a method of manufacturing the same. The device includes a gate oxide layer formed on a silicon substrate; a conductive spacer and a dummy spacer, which are formed on the gate oxide layer and separated apart from each other, the conductive spacer and the dummy spacer having round surfaces that face outward; a pair of insulating spacers formed on a sidewall of the conductive spacer and a sidewall of the dummy spacer which face each other; an ONO layer formed in a self-aligned manner between the pair of insulating spacers; a conductive layer formed on the ONO layer in a self-aligned manner between the pair of insulating spacers; and source and drain regions formed in the silicon substrate outside the conductive spacer and the dummy spacer.

Local SONOS-type nonvolatile memory device and method of manufacturing the same

The present invention includes a method of fabricating a non-volatile memory device having two transistors for two-bit operations to improve electron trapping efficiency and integration degree of the non-volatile memory device, and a method of driving the non-volatile memory device. The EEPROM device according to the present invention comprises a silicon substrate including a first and a second channel area, a first and a second conductive gate on the first and the second channel area, respectively, facing each other, a first and a second insulation layer in the bottom of the first and the second gate, and a first and a second junction area of a second conductive type between the first and the second channel area overlapping with the first and the second conductive gate.

Growing community of inventors

Seongnam-si, South Korea

Seong-Gyun Kim