International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Globalfoundries Inc.

Infineon Technologies North America Corp.

Seong-Dong Kim

Brent A Anderson

Bruce Bennett Doris

Rajasekhar Venigalla

Oh-Jung Kwon

Huilong Zhu

Deok-Kee Kim

Terence B Hook

Albert Manhee Chu

Qintao Zhang

Yong-Kuk Jeong

Myung-Hee Na

Young-jun Kim

O Sung Kwon

Thomas A Wallner

Jin Zheng Wallner

Bong-Seok Suh

Zhijong Luo

Dong-Hee Yu

Zhijiong Lou

A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.

Vertical transistor fabrication and devices

A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.

Vertical transistors with merged active area regions

A FinFET semiconductor device fabrication process includes forming a plurality of FinFET fins upon a semiconductor substrate, forming a first dielectric layer upon the semiconductor substrate so that an upper surface of the first dielectric layer is coplanar with upper surfaces of the FinFET fins, forming a plurality of dummy gates upon the FinFET fins and the first dielectric layer orthogonal to the FinFET fins, revealing the FinFET fins by removing first portions of the first dielectric layer from source-drain regions, removing the dummy gates, and subsequent to the removal of the dummy gates, revealing the FinFET fins by removing second portions of the first dielectric layer from channel regions.

FinFET formation with late fin reveal

A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.

Asymmetric source/drain junctions for low power silicon on insulator devices

The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

Dual stress STI

Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance

The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.

A method for driving a pointing device of a computer system is provided. In the method, a pointer is positioned in a user interface area for performing a specific command such as an icon, a menu bar, and a menu button. If the pointer is moved from the user interface area to a specific area over a predetermined distance, an amount of the position change of the pointer is detected and if the amount thereof corresponds to a button click of the pointing device, the same pointing signal as that of a corresponding button click is generated. It is therefore possible to perform the same function as a button click when the pointer is moved in a specific direction over a predetermined distance without using a button of the pointing device. Thus, a user is able to more conveniently use the pointing device, and changing a holding form while clicking the button of the stylus can be advantageously reduced or suppressed.

Method and apparatus for driving pointing device of computer system

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Lagrangeville, NY, United States of America

Seong-Dong Kim