Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Seong-Do Kim

Hyun Kyu Yu

Mun Yang Park

Seon-Ho Han

Pil Jae Park

Yong-Sik Youn

Sang-Gug Lee

Ja Yol Lee

Hee-Bum Jung

Cheon-Soo Kim

Won-Chul Song

Young-Jun Kim

Nam-soo Kim

Byung-Do Yang

Sung Chul Woo

Chung-Wook Suh

Pil-Jae Park

Ki-Hyuk Sung

Sung-Chul Woo

Lee-Sup Kim

Provided is a pulse radar device including: a TX unit configured to emit a TX pulse according to a single TX clock signal; a multiple-RX units configured to receive echo pulses received through a plurality of RX antennas according to multiple RX clock signals; a pulse radar driving unit configured to generate the single TX clock signal and the multiple RX clock signals using a reference clock signal. The pulse radar driving unit provides the single TX clock signal and the multiple RX clock signals for the TX unit and the multiple-RX unit. The pulse radar driving unit adjusts an RX clock-to-clock delay that is the delay between the multiple RX clock signals so as to adjust a directivity of the multiple-RX unit, and a TX-to-RX delay between the single TX clock signal and the multiple RX clocks signals so as to adjust a detection range.

Pulse radar device and operating method thereof

A pulse radar apparatus is disclosed. The pulse radar apparatus includes a pulse generation unit, a receiver unit, a synchronization unit, and a switch unit. The pulse generation unit generates a pulse based on a transmission trigger signal having a transmission pulse repetition period, and sends the pulse to a target via a transmission antenna. The synchronization unit generates the transmission trigger signal using an external reference clock, provides the transmission trigger signal to the pulse generation unit, and generates a plurality of clock signals having a time delay with respect to the transmission pulse trigger signal using the external reference clock. The switch unit selects any one clock signal from the plurality of clock signals in response to an external selection signal, and provides the selected clock signal to a receiver unit which utilizes a sampler with provided sampling clocks.

Pulse radar apparatus

Disclosed is a pulse-signal recovering device with a time-interleaving scheme. Exemplary embodiments of the present invention can improve receive performance of a radar so as to shorten pre-scanning time for roughly determining presence and absence of objects and time consumed to recover received pulse signals in the radar receiver with the sub-sampling scheme by simultaneously sensing signal levels of the received pulse signals at several positions and improve a signal to noise ratio by increasing an averaging rate with respect to the number of same received pulses.

Pulse-signal recovering device with time-interleaving scheme

Disclosed is a fractional digital phase locked loop with an analog phase error compensator. The digital phase locked loop with an analog phase error compensator can reduce excessive power consumption and power noise and transient current noise while increasing phase error detection resolution by performing fractional phase error detection and compensation through the analog phase error compensator.

Fractional digital PLL with analog phase error compensator

The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e., coarse-quantized ROM, coarse-error ROM, fine-quantized ROM and fine-error ROM.

Method for dividing ROM and DDFS using the same method

An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP without needing additional power consumption caused by improving the linearity. The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.

Automatically gain controllable linear differential amplifier using variable degeneration resistor

The present invention relates to a fault detection and automatic recovery apparatus of write-read pointers in FIFO. While storing effective data in a register in writing performance, the apparatus does not unconditionally enable a FULL.sub.-- FLAG signal allotted to the register but confirms the relation of write-read pointers at that time and the EMPTY.sub.-- FLAG signal of a register at which the read pointer is situated and detects the error of FIFO. By selectively enabling the FULL.sub.-- FLAG signal of the register according to the result of detection, it automatically restores the FIFO functions without unnecessary re-initialization or the discontinuation of data transmission attributable thereto.

Fault detection and automatic recovery apparatus or write-read pointers

A frame synchronizing device for discriminating a time slot location for each channel of time-division multiplexed signals is disclosed. The frame synchronizing device according to the invention processes time-division multiplexed signals in parallel in a STM-4C(Synchronous Transport Module-4 Concatenation) of the Broadband Integrated Service Digital Network according to the ITU-T recommendation, such that the searching of frame synchronization can be achieved by detecting frame bytes on data being received at a high speed in the STM-4C structure to align the bytes based on the detected time interval, converting the frame data into the 8-bits parallel data and then detecting, in sequence, the frame bytes at a lower speed clock being divided by 8, thereby providing a simplified, less power consumptive frame synchronizing device in the STM-4C structure according to the ITU-T recommendation.

Growing community of inventors

Daejeon, South Korea

Seong-Do Kim