Electronics and Telecommunications Research Institute

Seong Do Kim

Hyun Kyu Yu

Mun Yang Park

Ja Yol Lee

Cheon Soo Kim

Pil Jae Park

Jang Hong Choi

Byung Hun Min

Sung Chul Woo

Jae Hoon Shim

Mi Jeong Park

Sang Gug Lee

Young Jae Lee

Song Cheol Hong

Hee Bum Jung

Seon Ho Han

Hyun Ho Boo

Jung Woo Park

Myung Shin Kwak

Ki Su Kim

Sun Bo Shim

Hoai Nam Nguyen

Disclosed are a pulse radar apparatus and an operating method of the pulse radar apparatus, the pulse radar apparatus including a transmitter configured to receive a reference signal as a transmission clock signal, and transmit a transmission pulse to an object based on the transmission clock signal, a negative feedback loop configured to delay the reference signal and output the delayed reference signal as a reception clock signal, and a receiver configured to restore, based on the reception clock signal, a reflection pulse received in response to the transmission pulse being reflected from the object, wherein the negative feedback loop is configured to generate a delay control signal using the reference signal and a predetermined waveform signal generated by a waveform generator, delay the reference signal based on the delay control signal, and adjust the delay control signal by controlling the waveform generator to change the predetermined waveform signal.

Pulse radar apparatus and operating method of pulse radar apparatus

A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and FIR-filtering the decimated signal.

Direct conversion receiver including a charge area decimation filter

An apparatus and method for identifying a human being and an animal are disclosed to properly identifying whether or not a target is a human being or an animal. The apparatus for distinguishing between a human being and an animal includes: a target stimulation unit generating a stimulation signals for selectively stimulating the senses of a human being and an animal and providing the generated stimulation signal to a target; and a target identifying unit detecting the reaction of a target to the simulation signal to identify whether or not the target is a human being or an animal.

Apparatus and method for distinguishing between human being and animal using selective stimuli

A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.

Pulse radar receiver

A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

Digital RF converter, digital RF modulator and transmitter including the same

An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency.

Time-to-digital converter and all digital phase-locked loop including the same

An apparatus and method for removing an interference signal using a selective frequency phase converter are disclosed. The apparatus for removing an interference signal using a selective frequency phase converter includes: a first phase converter configured to convert a phase of a received RF signal to differentially output first and second signals having a phase difference of 180&#xb0; from each other; a second phase converter configured to receive the first signal and selectively convert the phase of a particular frequency band; a third phase converter configured to receive the second signal and selectively convert the phase of a particular frequency band; a timing controller configured to correct a signal delay time between the output from the second phase converter and that of the third phase converter; and an adder configured to add an output from the second phase converter and an output from the third phase converter, wherein the second and third phase converters phase-convert the first and second signals such that the phases of the signals of the particular frequency bands do not have a phase difference of 180&#xb0; from each other.

Apparatus and method for removing interference signal using selective frequency phase converter

A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

Frequency calibration loop circuit

There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Frequency synthesizer including a digital lock detector

Digital lock detector and frequency synthesizer using the same

Provided is an apparatus for automatic gain control (AGC) widely used in a receiver of a wireless communication system. The receiver of a wireless communication system includes: a step variable gain amplifier and an analog variable gain amplifier disposed in the path of a wireless signal and amplifying the wireless signal; an analog gain control unit for generating a gain control voltage for feedback-controlling an amplification value of the analog variable gain amplifier; a digital gain control unit for receiving the control voltage and generating a digital code determining an amplification value of the step variable gain amplifier. The apparatus for AGC constituted as described above can reduce power consumption and the number of devices by efficiently running an AGC loop in an analog domain, and can be embodied at low cost in a structure appropriately controlling the step gain amplifier and the analog gain amplifier.

Apparatus for automatic gain control and wireless receiver employing the same

A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

Growing community of inventors

Daejeon, South Korea

Seong Do Kim