Hynix Semiconductor Inc.

Skhynix Inc.

Snu Rdb Foundation

Korea Advanced Institute of Science and Technology

Seoul National University

Ahnlab, Inc.

Hojeon Limited

Seong Cheol Kim

Chang Jun Park

Sung Min Kim

Kwon Whan Han

Ha Na Lee

Jong Hoon Kim

Min Suk Suh

Hyeong Seok Choi

Seung Hyun Lee

Seung Taek Yang

Myung Geun Park

Byoung Hoon Kim

Jae Hong Lee

Jung Kyu Lee

Tac Keun Oh

Young Chul Park

Sang Joon Lim

Eun Suk Suh

Jeong Sik Choi

Joo O Song

Jang S Han

Sung Hoon Ahn

Woo Kyun Jung

Seung Hee Jo

Disclosed are modularized garment manufacturing method and system for small quantity batch production of garments. Basic components constituting an ordered garment are generated by analyzing shape graphic data of the ordered garment. For each basic component, basic patterns are generated for each dimension of the ordered garment. The basic patterns are compared with reference garment patterns stored in a garment pattern database to determine a pattern category of each basic pattern. Based on the pattern category of the basic patterns and information on garment production lines currently in operation, subdivided work modules are determined for each basic pattern. A configuration of modular sewing process lines, which include module processing lines for manufacturing the working modules and component-joining process lines for completing production of the ordered garment by joining the basic pattern products produced in each module processing line, is designed based on operation information of a garment production line.

Modularized garment manufacturing method for small quantity batch production of garments and modularized garment manufacturing system

An apparatus for connecting to an update server includes an update unit configured to connect to the update server over a network using a pre-stored domain name address of the update server and an IP address acquisition unit configured to acquire an IP address of the connected update server. The IP address acquired by the IP address acquisition unit is stored as a trusted IP address in a storage unit. The apparatus further includes a reconnection processing unit configured to fetch the trusted IP address of the update server and try connecting to the update server using the trusted IP address in the case of failure to connect to the update server using the pre-stored domain name address.

Method and apparatus for connecting to server using trusted IP address of domain

A bonding structure of a semiconductor package includes: a first conductive member configured to transmit an electrical signal; and a bonding pad configured to be electrically coupled to a surface of the first conductive member and comprising a plurality of sub bonding pads.

Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package

A method and an apparatus for estimating a long-term transfer rate of a terminal are provided. The method for estimating the long-term transfer rate includes: calculating a burst transfer rate of each pilot signal which is transmitted from a base station to a target terminal to calculate a long-term transfer rate; and calculating a long-term transfer rate of the target terminal using distribution of the calculated burst transfer rates and the number (N) of terminals that are serviced by the base station.

Method and apparatus for estimating long-term transfer rate of terminal

A semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface, a chip pad disposed on the first surface of the substrate, and a through-silicon via (TSV) including a plurality of sub vias electrically connected to the chip pad at different positions.

Semiconductor chip, semiconductor package, and method for manufacturing semiconductor chip for reducing open failures

A stacked semiconductor package includes a plurality of semiconductor chips each including a substrate having one surface, the other surface which faces away from the one surface and side surfaces which connect the one surface and the other surface, through-silicon vias which pass through the one surface and the other surface of the substrate, repair pads which are exposed on the side surfaces of the substrate, and wiring lines which electrically connect the through-silicon vias with the repair pads, the plurality of semiconductor chips being stacked such that through-silicon vias of the semiconductor chips are connected with one another; and interconnections electrically connecting the repair pads of the semiconductor chips.

Stacked semiconductor package

A semiconductor chip and semiconductor package with stack chip structure include align patterns. The align patterns are formed of magnetic materials having opposite polarities on the top and bottom of the semiconductor chip. Thus, when the plurality of chips are stacked on the substrate in order for the packaging, the semiconductor chips may be exactly aligned by the magnetic force between the align patterns of the vertically stacked chips. The semiconductor package includes a plurality of stacked semiconductor chips and a filling material. Each of the stacked semiconductor chips includes a semiconductor substrate having a first surface and a second surface, wherein a circuit pattern such as a bonding pad is formed on the first surface, and a first align pattern formed on the first surface of the semiconductor substrate, wherein the first align pattern is formed of a magnetic material.

Semiconductor chip and semiconductor package with stack chip structure

A wireless localization technology using efficient multilateration in a wireless sensor network is disclosed. After calculating estimated distances from each of at least three reference nodes to a blind node using received signal strength of wireless signals that the at least three reference nodes received from the blind node, the estimated location of the blind node is obtained through multilateration using the calculated estimated distances. To correct error in the estimated location, the estimated distances are used, and the error correction direction and error correction distance for the estimated location are calculated by applying a largest weight to the reference node closest to the estimated location. The error of the estimated location is corrected by move the estimated location of the blind node by the calculated error correction direction and error correction distance. Calculation for the error correction is very simple and fast.

Wireless localization method based on an efficient multilateration algorithm over a wireless sensor network and a recording medium in which a program for the method is recorded

A semiconductor package comprises a semiconductor chip, through electrodes and cooling parts. The semiconductor chip has bonding pads on an upper surface thereof. The through-electrodes are formed in the semiconductor chip. The cooling parts are formed in the semiconductor chip and on the upper surface of the semiconductor chip in order to dissipate heat.

Semiconductor package

A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

Semiconductor package module

A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same

A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate.

Stack package

A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a height that increases from edges toward a center of the warpage compensating part so that an upper surface of the warpage compensating part facing away from the first surface of the body part is convex upward. The warpage compensating part comprises conductive layer patterns formed over the first surface of the body part to be electrically connected to the connection pads; and a solder resist formed over the first surface of the body part so as to expose the conductive layer patterns. The height of the solder resist gradually increases from both edges toward a center of the solder resist.

Printed circuit board

A semiconductor chip includes a semiconductor chip body, a through-silicon via and a silicon pattern. The semiconductor chip body has a first surface and a second surface facing away from the first surface. The through-silicon via is formed to pass through the semiconductor chip body and has a metal layer and an insulation layer which protrude from the second surface. The silicon pattern is formed on a sidewall of the protruding through-silicon via.

Growing community of inventors

Seoul, South Korea

Seong Cheol Kim