Korea University Research and Business Foundation

Skhynix Inc.

Korea University Industrial Academic Collaboration Foundation

Samsung Electronics Co., Ltd.

Mewtel Technology Inc.

Seon Wook Kim

Ho Kwon Kim

Jae Yung Jun

Kyu Hyun Choi

Young Sun Han

Chang Hyun Kim

Thi Huong Giang Nguyen

Won Joon Lee

Wonjun Lee

Won Seok Lee

Il Han Park

Changhyun Kim

Jong-ok Kim

Hokyoon Lee

Miseon Han

Byung Gueon Min

Peter Harliman

Seok Joong Hwang

Yoonah Paik

Seok-Young Kim

An embodiment of the present invention provides a processing-in-memory memory device comprising: a memory bank including a memory array for receiving a memory request from a memory controller, and a PIM engine for executing processing-in-memory according to the PIM instruction; and a processing-in-memory (PIM) control unit for controlling the processing-in-memory of the PIM engine by identifying a PIM instruction corresponding to the memory request, and storing addressing mode selection information for selecting one among an indirect address and a direct address according to the identified PIM instruction, wherein when the indirect address is used, the PIM control unit uses a register value of the processing-in-memory control unit as a base register value, reads an immediate value in the PIM instruction, a register value of the PIM engine, or an offset value of the memory bank, and generates an effective address for the processing-in-memory in an indirect addressing mode.

Processing-in-memory memory device and method for performing indirect addressing in the same

A Processing-In-Memory (PIM) computing system and a PIM computation offloading method thereof perform PIM computation offloading using a DMA engine. The DMA engine is configured to process a transaction by respectively performing descriptor requests and PIM requests for one or more descriptors stored in a memory, in response to a memory request of a CPU. The memory includes a PIM unit and a memory array, which memory array may be a DRAM. In response to the PIM requests, the PIM unit performs PIM operations using information included in data provided to the DMA engine in response to the descriptor requests.

PIM computing system and PIM computation offloading method thereof

Disclosed is a memory device including a plurality of memory banks, each of which performs an operation based on first operand data including pieces of first unit data and second operand data including pieces of second unit data and a processing in-memory interface unit (PIM IU) that delivers signals for an operation request to the plurality of memory banks. Each of the plurality of memory banks includes a memory cell array configured to store one of the pieces of first unit data and a PIM engine that reads the one of the pieces of first unit data from the memory cell array, reads the pieces of second unit data broadcast to the plurality of memory banks, and generates an operation result by performing an operation based on the one of the pieces of first unit data and the pieces of second unit data.

Memory device performing in-memory operation and method thereof

A Processing-in-Memory (PIM) computing system and a memory controller provide improved memory traffic efficiency and improved PIM operation efficiency by increasing a burst length of a PIM operation relative to a general memory request. In embodiments, the increased burst length allows the PIM operation to be performed in units of pages, wherein a page is management unit of a memory used in the PIM operation.

PIM computing system and memory controller thereof

A semiconductor device may include a memory controller, which may include a request queue storing requests. Requests include a memory request including a read request to a memory device or a write request to the memory device, and a process in memory (PIM) request requesting a processing operation in the memory device. The memory controller may also include a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue, a command queue storing a memory command and a PIM command output from the command generator, and a command scheduler configured to control output order, output timing, or both of a memory command and a PIM command stored in the command queue.

Memory device including a processing circuit, memory controller controlling the memory device and memory system including the memory device

Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.

Memory management system and method thereof

Disclosed are an analyzing system for managing an information storage table and a control method thereof. That is, each of the physical basic regions, which are units of hashing an information storage position, is divided into a plurality of physical sub regions having same size. Then, a combination of virtual basic regions which satisfy a predetermined target value is checked from all configurable combinations and a hash value related with the combination of the virtual basic regions which satisfies the checked target value is stored in a predetermined region of a memory. Therefore, even though an information storage space required for every unit region is overloaded, when there is an extra information storage space in another region, the information storage space having an extra space is used to maximize efficiency of the information storage space.

Analyzing system for managing information storage table and control method thereof

Disclosed are a memory apparatus having a plurality of information storage tables managed by separate virtual regions and a control method thereof. That is, a fault repair is applied in a memory system having a plurality of information storage tables managed by a separate virtual region, so that the entire information storage space is uniformly used for every region to improve a performance of the entire system and maximize efficiency of the information storage space by utilizing the information storage space.

Memory apparatus having plurality of information storage tables managed by separate virtual regions and control method thereof

A method for extending the lifetime of a resistive change memory includes generating data and hash candidates by shuffling bit positions of write data with the hash candidates in response to a write request for the resistive change memory, calculating Hamming distances of the generated data and hash candidates from stored data and a stored hash, matching stuck data at a predetermined bit in the resistive change memory with the generated data and hash candidates when the stuck data is at the predetermined bit, and excluding mismatched data and hash candidates that are mismatched with the stuck data among the generated data and hash candidates, finding a data and hash candidate with the shortest Hamming distance among the matched data and hash candidates, and choosing the found data and hash candidate as an encoded data and hash, and storing the encoded data and hash in the resistive change memory.

Method for extending lifetime of resistive change memory and data storage system using the same

Provided are a memory apparatus for applying fault repair based on a physical region and a virtual region and a control method thereof. That is, the fault repair is applied based on the physical region and the virtual region which use an information storage table of a virtual basic region using a hash function, thereby improving efficiency of the fault repair.

Memory apparatus for applying fault repair based on physical region and virtual region and control method thereof

This invention relates to a data transmission method in a passive communication system being wirelessly powered up and being passively operable, without using its own power, for data transmission and reception, such as in a passive RFID (Radio Frequency IDentification) communication system, which is capable of effectively configuring a message transmitted by a passive device, thereby providing improved transmission efficiency.

Data transmission method in passive communication system

The present invention is directed to a method and system for translating a high-level language (HLL) code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL which requires no modification in the original HLL source code, while supporting a cross call between software and hardware, and even recursive calls in hardware. The system includes: a HLL-to-HLL source translator which reads user programming directive from a translation-targeted high-level language code marked with the user directive, and separates the translation-targeted high-level language code into a hardware code part and a software code part; a main compiler which compiles the software code part; a HLL-to-HDL translator which includes the front-end and middle-end of the main compiler and a HDL backend; a main core which executes the compiled software code part; and a dedicated hardware which executes the HDL code.

System and method for translating high-level programming language code into hardware description language code

The present invention is directed to a method and system for translating a high programming level language code such as C, C++, Fortran, Java or the like into a HDL code such as Verilog or VHDL. The system includes: a C-to-C source translator which reads user API from a translation-targeted high level language code marked with the user API, separates the translation-targeted high level language code into a hardware code part and a software code part, and stores the hardware code part and the software code part in separate files; a main compiler which compiles the stored software code part; a translator which translates the stored hardware code part into a HDL code including one or more block modules and one top module; a main core which executes the compiled software code part; and a dedicated hardware which executes the HDL code.

System and method for translating high programming level languages code into hardware description language code

A block interleaving apparatus for block interleaving M-bit input streams to be transferred with a modulus k using a mixed radix system in a multi-band orthogonal frequency division multiplexing communication system, including an array processor having an array including M cells in which the number of columns is k and the number of rows is M/k. The array processor inputs the input streams from the bottom-right cell up to the top-left last cell in the horizontal direction, and, after the first bit of the input streams reaches the last cell, generates interleaved output streams by changing the output of the array processor from horizontal direction to vertical direction.

Growing community of inventors

Gyeonggi-do, South Korea

Seon Wook Kim