Skhynix Inc.

Seon Woo Hwang

Jae Woo Lee

Jung Hwan Ji

In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

Error correction code circuit and semiconductor apparatus including the error correction code circuit

The present technology may include an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data, and a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and to share substantially the same signal path in generating the first delay data and in generating the second delay data.

Error correction code circuit and semiconductor apparatus including the same

The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

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Icheon-si, South Korea

Seon Woo Hwang