Samsung Electronics Co., Ltd.

Seon-Taek Kim

Chan-Ik Park

Sung-up Choi

Won-Moon Cheon

Byoung-Kook Lee

Ji-Soo Kim

Byung-Gook Kim

Yoon-young Kyung

In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.

Flash memory device with multi-level cells and method of performing operations therein according to a detected writing patter

Flash memory device with multi-level cells and method of writing data therein

Provided are a portable storage device and a method of managing a resource of the portable storage device. The method includes converting a first DRM application into a ready status from an idle status if task processing of the first DRM application is required, and converting the first DRM application into a pending status and a second DRM application into the ready status from the idle status if task processing of the second DRM application is required.

Portable storage device and method of managing resource of the portable storage device

A circuit is operated to detect unstable memory cells from among a plurality of memory cells in at least one page. A determination is made from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable. Responsive to determining that a read error occurs that is correctable, a further determination is made as to whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable.

Memory systems and methods of detecting distribution of unstable memory cells

A hybrid flash memory device includes an array including a first area and a second area having a larger number of stored bits per cell than the first area. The device includes a hidden area including a first reserved block area and a second reserved block area, wherein the first reserved block area includes a plurality of first memory blocks having the same number of stored bits per cell as the first area, the second reserved block area includes a plurality of second memory blocks having the same number of stored bits per cell as the second area, and a flash translation layer configured to replace a bad block generated in the first main area with the first memory block and replace a bad block generated in the second main area with the second memory block, wherein the flash translation layer flexibly assigns functions of the first memory blocks or the second memory blocks depending on whether the first and second memory blocks are all used.

Growing community of inventors

Suwon-si, South Korea

Seon-Taek Kim