Samsung Electronics Co., Ltd.

Seon-Kyoo Lee

Byung-Hoon Jeong

Jeong-Don Ihm

Young-Don Choi

Dae-Woon Kang

Anil Kavala

Dae-hoon Na

Sang-Lok Kim

Tae-Sung Lee

A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

Method and circuit for self-training of a reference voltage and memory system including the same

An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.

Apparatus and method of transmitting and receiving data, and semiconductor package including the same

A semiconductor device includes a reference voltage generator configured to output a reference voltage. The reference voltage generator includes a boosting code circuit and a first digital-analog converter (DAC). The boosting code circuit includes a first boosting pulse generator configured to generate a first boosting pulse and a first boosting code controller configured to output a first boosting code based on a reference code and the first boosting pulse. The first DAC is configured to output the reference voltage by converting the first boosting code. The first boosting code has a first code value different from the reference code when the first boosting pulse has a first logic level, and the first boosting code has the same value as the reference code when the first boosting pulse has a second logic level opposite to the first logic level.

Reference voltage generator and semiconductor device including the same

A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

Reception interface circuits supporting multiple communication standards and memory systems including the same

An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.

Equalizer circuit and integrated circuit including the same

A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).

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Hwaseong-si, South Korea

Seon-Kyoo Lee