Skhynix Inc.

Samsung Electronics Co., Ltd.

Chung Jin Biotech Co., Ltd

Jeonju University Office of Industry-University Cooperation

Seon Ju Lee

Jae Min Lee

Min Hwan Moon

Jong Su Jeon

Yong Kwon Kim

Chul Yong Cho

Kyung Mok Yoo

Dong Kyu Lee

Seung Geol Baek

Jae Hyun Yoo

Ki Tae Kim

Sun Min Lee

Ae Ryun Kim

In Ho Jung

Young Seok Lee

Simon Edward Ireland

Nam Soo Park

Hyung Kwen Ham

Ji Hoon Choi

Ji Yeon Lee

Youn Tae Shin

Dong Hyun Lee

Tae-In Eom

Byoung Mok Kim

Bok Hyun Jang

Jeong Hyun Lee

June Hyuck Choi

Yukyung Lee

Peng Qiang

Da Seul Lee

Jung Kyung Kwack

Wan Gi Park

Kab Jin Jun

Yang Yeol Gu

Kang Rak Kwon

Eun Gu Lee

Chui Yong Cho

Jeong Sun Park

You Min Ji

Eui Kyung Kim

Geon Woo Kim

Dong Min Bhan

Yeon Hee Shin

Chang Zhe Shen

Ha Young Won

Choul Goo Kim

Moon Young Choi

Seung Ju Kim

Jung Keun Park

Chul Yoong Park

Jung Chul Han

Jin Hae Chang

Simon Ireland

Min Seok Choi

Dong Yeong Kim

Cho Min Lee

Hong Kun Kim

A memory device includes: a plurality of memory blocks each including a plurality of word lines, a control operation circuit configured to perform a read operation on each of the plurality of word lines, and a control logic configured to: store a plurality of default levels, which respectively correspond to the memory blocks, in an information storage region therein, control the control operation circuit to perform one of a first read operation using a selected default level corresponding to a selected block and a second read operation using an adjusted level smaller than the selected default level, reset the adjusted level to the selected default level when a number of times that the second read operation is passed is greater than a number of times that the first read operation is passed, by a reference number of times or more, and store the reset level in the information storage region.

Memory device and memory system for using read compensation scheme and operating method of the same

A data storage device may include a plurality of system resources, a buffer memory device and a memory controller. The buffer memory device may include a buffer memory allotted to the system resources. The memory controller may allocate the buffer memory based on performance requirements that are set in each of the system resources.

Data storage device for guaranteeing that system resources meet performance requirements, method of operating the same, and memory controller for the same

The present disclosure relates to a storage device that optimally maintains a size of debugging data. Disclosed is a memory controller, including a first interface may communicate with a first external device; a second interface may generate a signal for controlling an operation of a second external device; a first volatile memory buffer; and a processor may generate and store the telemetry log data in the first volatile memory buffer; move and store the telemetry log data stored in the first volatile memory buffer to a first non-volatile memory buffer, when a size of the telemetry log data stored in the first volatile memory buffer is greater than or equal to a threshold size; and set the threshold size based on at least one among a number of telemetry logs stored in the first volatile memory buffer and a rising momentum of the number of the telemetry logs.

Storage device for collecting optimal debugging data and system including the storage device

Disclosed herein is a washing machine that includes a tub disposed in a main body of the washing machine to store water. A circulation apparatus includes a circulation pump operable to circulate the water in and out of the tub. A detergent supply apparatus is coupled to the circulation apparatus to discharge detergent to the circulation apparatus so that operation of the circulation pump causes the discharged detergent to be supplied to the tub.

Automatic detergent supply apparatus and washing machine having the same

Provided herein may be a memory system and a method of operating the same. A memory controller may include a latency monitoring component configured to generate information about a number of occurrences of over-latency exceeding a preset reference latency among latencies each indicating a time amount required from a time point at which first command is received from an external device to a time point at which a completion response to the first command is transmitted to the external device during a first period, and a completion response controller configured to determine a first target latency based on the information about the number of occurrences of over-latency, and provide, during a second period following the first period, the external device with a completion response to a second commands provided from the external device after the first target latency has elapsed.

Memory system for controlling latency and method of operating the same

Provided herein may be a memory controller and a memory system including the same. The memory controller may include a plurality of control cores configured to control a plurality of zone blocks respectively corresponding to logical address groups provided by a host, a buffer memory configured to store information about a zone group including zone blocks which are controlled by different control cores among the plurality of zone blocks, the information about zone group being generated based on information about an available space in each of the plurality of zone blocks, and a wear-leveling controller configured to control the plurality of control cores to perform a global wear-leveling operation of swapping pieces of data between the zone blocks included in the zone group based on a wear-level of the plurality of zone blocks.

Memory controller for performing wear-leveling and memory system including the same

A memory system may include: a memory device including at least one word line and at least one memory cell coupled to the word line, and a controller including a write buffer configured to store a program command and data received from a host, the controller suitable for controlling a program operation of storing the data in the word line based on the program command, setting state check time of the word line during a performance period of the program operation, and checking a state of the word line according to a timeout signal generated based on the set state check time.

Method and system for dynamically adjusting state check start time of word lines

A storage device may include: a plurality of memory dies; and a memory controller for receiving a first read request from a first function, controlling at least one memory die to perform a read operation according to the first read request, and controlling, when receiving a second read request from a second function in the course of the read operation according to the first read request, the at least one memory die to suspend the read operation according to the first read request and to perform a read operation according to the second read request based on a result obtained by comparing performance requirement information of the second function with residual time information of the second read request, which is determined according to a performance degree of the read operation being performed according to the first read request.

Storage device, electronic device including the same, and operating method thereof

A storage device may fetch commands from a plurality of command queues. The storage device may determine a policy for fetching commands from the plurality of command queues as a first policy or a second policy on the basis of the state of a target command queue among the plurality of command queues. The policy may control an order in which commands are fetched from the plurality of command queues.

Storage device determining a policy for fetching commands from a plurality of command queues, and method thereof

A memory system comprising: a memory device having a nonvolatile specific storage space configured to store workload information including groups of parameter values, grouped respectively corresponding to a plurality of workload classes in a table form, and a controller configured to detect a ratio of a set command inputted from an outside in a set operation mode, select one of the workload classes as a detected class, load, from the specific storage space, one of the groups corresponding to the detected class, process the set command under an execution condition determined by applying the loaded group, and update the group corresponding to the detected class with parameter values inputted from the outside.

Memory system for optimizing parameter values according to workload class and data processing system including the same

A memory system may include a memory device including a plurality of memory areas each configured by a plurality of memory blocks; and a memory controller configured to generate zones each including at least one memory block selected from at least one of the memory areas included in the memory device, manage configuration information for each generated zone, sequentially store data from a first storage location of an open zone among the generated zones during a write operation on the open zone according to an external request, and determine a number of active target memory areas associated with the open zone on a basis of configuration information of the open zone.

Memory system and method for operating the same

A method for operating a performance optimization device of memory system is provided, the method including determining N, where N is a natural number greater than 0, candidate performance parameter values for a performance parameter of the memory system; calculating N objective function results for an objective function defined for the memory system; and determining an additional candidate performance parameter value for the performance parameter of the memory system, based on the N candidate performance parameter values and the N objective function results.

Performance optimization device of memory system and operating method thereof

A memory system may wait to receive one or more read commands from a reference time point, and read data, requested by the one or more read commands, from the memory device in response to a determination that it is possible to simultaneously read data divided and stored, as an M number of data units, in an M number of planes among a plurality of planes in response to the one or more read commands or that a maximum read wait time has elapsed from the reference time point, M being a natural number.

Memory system for determining read wait time, memory controller, and method for operating memory system

The present technology relates to an electronic device. According to the present technology, a memory controller may include a latency monitor and an operation controller. The latency monitor may count an over-latency count value representing a number of over-latencies exceeding a reference value among latencies for requests from a host during each of a plurality of periods, calculate gaps which are difference values between the over-latency count values of the plurality of periods, and generate latency information including the over-latency count values and the gaps. The operation controller may determine, based on the latency info oration, whether each gap between at least two target periods among the plurality of periods exceeds a threshold value, and delay a response to the requests according to a determination result.

Memory controller and method of operating the same

A data storage device may include a storage including a plurality of storage regions each composed of a plurality of pages; and a controller. The controller is configured to select a plurality of target open regions from open regions among the storage regions on the basis of health information of the open regions, in each of which a programmed page and an unprogrammed page coexist, and perform control so that refresh operations for the respective target open regions are performed in a time-distributed manner.

Data storage device for refreshing data and operating method thereof

Growing community of inventors

Seoul, South Korea

Seon Ju Lee