Samsung Electronics Co., Ltd.

Seon-Bae Kim

Seung Hyun Song

Young Chai Jung

Mingyu Kim

Jinyoung Park

Heonjong Shin

Doohyun Lee

Chang Woo Sohn

Munhyeon Kim

Hyunho Park

Minchan Gwak

Yeonho Park

Min Cheol Oh

Youngchai Jung

Yong-Woo Lee

Kyung-Min Kim

Seong-Sik Choi

Joo-Woan Cho

Kyungin Choi

Hyun-Jin Kim

Seok-Hyun Nam

Moon-han Park

Chi-O Cho

Hyun-Chul Bae

Hee-Tae Kim

Cheol-Yong Noh

Du-Hwan Chung

Sang-Hyuck Yoon

Dong-hoon Khang

Dong-woo Kang

Dong-Chin Lee

So-Jin Ryu

Ji-ho Yoo

Min-Jeong Wang

A semiconductor device may include first and second active regions on a substrate, first and second active patterns on the first and second active regions, first and second source/drain patterns on the first and second active patterns, first and second silicide patterns on the first and second source/drain patterns, and first and second active contacts coupled to the first and second source/drain patterns. A lowermost portion of the first active contact is at a level higher than that of a lowermost portion of the second active contact. A thickness of the first silicide pattern is greater than that of the second silicide pattern.

Semiconductor device

A semiconductor device is disclosed. The semiconductor device may include a semiconductor substrate including a protruding active pattern, a first gate pattern provided on the active pattern and extended to cross the active pattern, a first capping pattern provided on a top surface of the first gate pattern, the first capping pattern having a top surface, a side surface, and a rounded edge, and a first insulating pattern covering the side surface and the edge of the first capping pattern. A thickness of the first insulating pattern on the edge of the first capping pattern is different from a thickness of the first insulating pattern on outer side surfaces of the spacer patterns.

Semiconductor device including a capping pattern

A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

A semiconductor device includes a substrate with an active region being provided with a channel pattern, a device isolation layer including a first part defining the active region and a second part surrounding a first portion of the channel pattern, an upper epitaxial pattern disposed on an upper surface of the channel pattern, a gate electrode surrounding a second portion of the channel pattern and extending in a first direction, a gate spacer on the gate electrode, an interlayer dielectric layer on the gate spacer, and an air gap between a bottom surface of the gate electrode and the second part of the device isolation layer. At least a portion of the air gap vertically overlaps the gate electrode. The second portion of the channel pattern is higher than the first portion of the channel pattern.

Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

Integrated circuit devices including a vertical field-effect transistor (VFET) and methods of forming the same

A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

Symmetrical two-dimensional fin structure for vertical field effect transistor and method for manufacturing the same

To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.

Method of manufacturing integrated circuit device

In a method of manufacturing a backlight assembly, a light reflective and heat-radiating sheet including a light reflective sheet layer to reflect light and a heat-radiating sheet layer are prepared. The heat-radiating sheet layer includes a coupling layer integrally formed with a surface of the light reflective sheet layer and heat-diffusing particles are dispersed in the coupling layer to diffuse heat provided from the exterior. The light reflective and heat-radiating sheet is disposed so that the coupling layer is adhered to a bottom plate of a receiving container. Thus, impurities may be prevented and/or reduced, and assembling efficiency may be improved.

Backlight assembly, display device having the backlight assembly and method of manufacturing the same

A fluorescent lamp includes a lamp body, a fluorescent layer and a discharge electrode. The lamp body has a discharge space in which ultraviolet light is generated. The fluorescent layer is formed on an inner surface of the lamp body to change the ultraviolet light into visible light. The discharge electrode is on an end portion of the lamp body to apply a voltage to the discharge space. A ratio of intensities of the visible light at wavelengths of about 545 nm and about 516 nm is about 1.32:1 to about 1.71:1. Therefore, color reproducibility and luminance may be improved.

Fluorescent mixture for fluorescent lamp, fluorescent lamp, backlight assembly having the same and display device having the same

Growing community of inventors

Hwaseong-si, South Korea

Seon-Bae Kim