Qualcomm Incorporated

Seokyong Oh

Jai N Subrahmanyam

Jinxia Bai

Chinnappa K Ganapathy

Durk L Van Veen

Kevin Stuart Cousineau

Raghuraman Krishnamoorthi

Thomas Sun

Techniques for performing IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory having first and second sections, an encoder configured to process data in each of the first and second memory sections, an IFFT configured to process the encoded data in the first and second memory sections, and a post-processor configured to process the IFFT processed data in the first memory section while the IFFT is processing the encoded data in the second memory section, the post processor configured to operate at a different clock speed than the encoder or the IFFT.

IFFT processing in wireless communications

The various embodiments provide circuitry and methods for packing Log Likelihood Ratio ('LLR') values into a buffer memory in a compressed format which reduces the amount of buffer memory required. Various embodiments use a type of quantization which reduces the bit width of the LLR values that are stored, with the particular level of quantization depending upon the code rate of the data. The degree, pattern, and periodicity of bit width compression employed may depend upon the code rate of the received transmission. Bit width patterns use for LLR value quantization may be generated by a shift register circuit which provides an efficient mechanism for controlling an LLR packer circuit based upon the code rate of the received signal.

Method and apparatus for data quantization and packing with variable bit width and period

Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

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San Diego, CA, United States of America

Seokyong Oh