Samsung Electronics Co., Ltd.

Yonsei University

Bc Card Co., Ltd.

SeokWon Lee

Seokhyun Lee

Jongyoun Kim

Kyoung Lim Suk

Youn Ji Min

Hohyeuk Im

Young Soo Kim

Young Jun Hong

Chang Soon Park

Jongbo Shim

Hyunki Kim

Kyoungsei Choi

Joonsung Kim

Su-Min Park

Daesik Hong

Jongkook Kim

Eunseok Cho

Jung-Do Lee

JiSun Hong

Byoungwook Jang

Jaesik Lee

Gowoon Seong

Sokho Chang

Sameui Kwon

Choonghwan Yi

Jinwoo Park

Hyungsik Ju

JongKook Kim

A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area; a fan-in chip structure located in the through-hole, the fan-in chip structure comprising a first chip, a capacitor chip arranged to be apart from the first chip, and a second chip disposed on both the first chip and the capacitor chip; a redistribution structure arranged on a bottom surface of the package body and a bottom surface of the fan-in chip structure and including a redistribution element extending to the fan-out area; and an interconnect via arranged on a top surface of the package body and electrically connected to the redistribution element in the fan-out area.

Fan-out semiconductor package

A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 &#x3bc;m to about 0.5 &#x3bc;m, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

Method of fabricating semiconductor package

A method of fabricating a semiconductor package including forming a preliminary first insulating layer including a first opening, curing the preliminary first insulating layer to form a first insulating layer, forming a preliminary second insulating layer on the first insulating layer at least partially filling the first opening. The method includes forming a second opening in the preliminary second insulating layer at least partially overlapping the first opening. A sidewall of the first opening is at least partially exposed during forming the second opening. The preliminary second insulating layer is cured to form a second insulating layer. A barrier metal layer is formed along the sidewall of the first opening and along a sidewall of the second opening. A redistribution conductive pattern is formed on the barrier metal layer. A planarization process is performed to at least partially expose the second insulating layer.

Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.

Semiconductor package and method of fabricating the same

Disclosed are a Bluetooth communication method and system which enable a Bluetooth device to be connected to other terminals without a pairing process and data to be transmitted through Bluetooth communication when the Bluetooth device is paired with any of a plurality of terminals having the same device information. The Bluetooth communication method includes receiving, by a receiving unit in a central communication server, communication information from a first terminal when the first terminal and a Bluetooth device are paired, transmitting, by a transmitting unit in the central communication server, the communication information to a second terminal having the same device information as the first terminal, and establishing, by the second terminal, a communication channel with the Bluetooth device, without the pairing process, on the basis of the received communication information.

Method and system for bluetooth communication

A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.

Semiconductor device and method of manufacturing the same

Provided are a first hub corresponding to a first WBAN and a second hub corresponding to a second WBAN which may communicate with each other through a temporal connection. The temporal connection may decrease the usage of additional data, complexity, and power consumption that typically occurs due to mutual communication between different WBANs.

First hub and second hub communicating by temporal connection between different wireless body area networks (WBANs) and communication method thereof

Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Semiconductor chips having guard rings and methods of fabricating the same

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Seoul, South Korea

SeokWon Lee