Samsung Electronics Co., Ltd.

Seokil Kim

YouKeun Han

Tae-Hyung Kim

Young Nam Yun

Jonghyoung Lim

Huichong Shin

Hoiju Chung

Sang-Yeol Lee

Yongjae Shin

A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.

Memory systems with ZQ global management and methods of operating same

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

Methods of operating buffered multi-rank memory modules configured to selectively link rank control signals

Buffered multi-rank memory modules configured to selectively link rank control signals and methods of operating the same

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Hwaseong-si, South Korea

Seokil Kim