Samsung Electronics Co., Ltd.

Seokhun Hyun

Young-Soo Sohn

Kyung-Soo Ha

Ki-Seok Oh

Donghun Lee

Changkyo Lee

Young-Hoon Son

Hyun-Yoon Cho

Daesik Moon

Junghwan Choi

A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Memory device, memory system, and operation method of memory device

Memory device performing ZQ calibration, memory system, and operation method of memory device

A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal.

Delay locked loop circuit and operation method thereof

Growing community of inventors

Seongnam-si, South Korea

Seokhun Hyun