Samsung Electronics Co., Ltd.

Seokhoon Kim

Pankwi Park

Choeun Lee

Seung Hun Lee

Jinbum Kim

Sujin Jung

Jungtaek Kim

Sihyung Lee

Dongsuk Shin

Yang Xu

Byeongchan Lee

Namkyu Cho

Kwan Heum Lee

Dongwon Kim

Kihyun Hwang

Keun Hwi Cho

Kyungin Choi

Dahye Kim

Sangmoon Lee

Min-Hee Choi

Myunggil Kang

Chul Kyu Kim

Seunghun Lee

Sunguk Jang

Sunyoung Lee

Kuntack Lee

Jung-Min Oh

Gyeom Kim

Yongsun Ko

Bonyoung Koo

Ryong Ha

Nam-Kyu Kim

Sangsu Kim

Yong-Jhin Cho

Sanggil Lee

Seojin Jeong

Edward Namkyu Cho

Jeongho Yoo

Minhee Choi

Moonseung Yang

Jinyeong Joe

Jaemun Kim

Ilgyou Shin

Haejun Yu

Kwanheum Lee

Keunhwi Cho

Kanghun Moon

Sumin Yu

Hyun-Kwan Yu

Youngdae Cho

Jongryeol Yoo

Kang Hun Moon

Dongmyoung Kim

Seong Hoon Jeong

Dong Chan Suh

Moon Seung Yang

Hyunjae Kang

Jeon Il Lee

Hanki Lee

Sungkeun Lim

Kyoungseob Kim

Yongmyung Jun

Jaeyoung Park

Dongchan Suh

Kwangsu Kim

Wonho Jang

Hyunkwan Yu

Sunghil Lee

Chung Geun Koh

Jieon Yoon

Dohyun Go

Yu-Jin Pyo

Edwardnamkyu Cho

A semiconductor device includes a substrate including a first active pattern, a first channel pattern on the first active pattern, the first channel pattern including first, second, and third semiconductor patterns spaced apart from one another and vertically stacked, a first source/drain pattern connected to the first to third semiconductor patterns, and a gate electrode on the first to third semiconductor patterns. The first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern, a second protrusion protruding toward the second semiconductor pattern, and a third protrusion protruding toward the third semiconductor pattern. A width of the second protrusion is greater than a width of the first protrusion. A width of the third protrusion is greater than the width of the second protrusion.

Semiconductor device including a vertically stacked channel pattern and method for manufacturing the same

A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

Semiconductor device and method for manufacturing the same

An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source/drain region in contact with one sidewall of the first nanosheet stack, and a second source/drain region in contact with another sidewall of the first nanosheet stack, wherein a greatest width of the first source/drain region is less than a greatest width of the second source/drain region in the second lateral direction may be provided.

Integrated circuit device including field-effect transistor with controlled sizes and configurations

A semiconductor device includes a substrate including a first region, a second region, and active regions extending in a first direction in the first region and in the second region; gate electrodes on the first region and the second region, the gate electrodes intersecting the active regions and extending in a second direction; a plurality of channel layers spaced apart from each other in a third direction on active regions of the active regions and encompassed by the gate electrodes, the third direction being perpendicular to an upper surface of the substrate; and first source/drain regions and second source/drain regions in portions of the active regions that are recessed on both sides of the gate electrodes, the first source/drain regions and the second source/drain regions being connected to the plurality of channel layers, wherein the first source/drain regions are in the first region, and the second source/drain regions are in the second region, wherein an end portion of each of the first source/drain regions in the second direction in a plan view includes a tip region protruding in the second direction, and wherein an end portion of each of the second source/drain regions in the second direction in the plan view extends flatly in the first direction.

Semiconductor device including source/drain regions having triangular tip regions

A semiconductor device includes a substrate that includes an active pattern, a channel pattern disposed on the active pattern, where the channel pattern includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, and a gate electrode disposed on the semiconductor patterns. The gate electrode includes a plurality of portions that are respectively interposed between the semiconductor patterns, and the source/drain pattern includes a buffer layer in contact with the semiconductor patterns and a main layer disposed on the buffer layer. The buffer layer contains silicon germanium (SiGe) and includes a first semiconductor layer and a first reflow layer thereon. A germanium concentration of the first reflow layer is less than that of the first semiconductor layer.

Semiconductor device including reflow layers

An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

Integrated circuit device

An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a SiGelayer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.

A semiconductor device may include a substrate including center and edge regions, active patterns on the substrate, channel patterns on the active patterns, source/drain patterns connected to the channel patterns, and gate electrodes on the channel patterns. Each of the source/drain patterns may include a buffer layer in contact with a corresponding one of the channel patterns and a main layer on the buffer layer. The main layer of each of the source/drain patterns may include first and second semiconductor layers, which may be sequentially stacked and contain germanium. A concentration of the germanium in the first semiconductor layer may be higher on the center region than on the edge region, and a concentration of the germanium in the second semiconductor layer may be lower on the center region than on the edge region.

Semiconductor device and method of fabricating the same

A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

Semiconductor device having a liner layer and method of fabricating the same

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1-xGex layer, where x≠0, and the inner blocking layer including a Si layer.

A semiconductor device includes a first active region, a second active region spaced apart from the first active region, a plurality of first channel layers disposed on the first active region, and a second channel layer disposed on the second active region. The semiconductor device further includes a first gate structure intersecting the first active region and the first channel layers, a second gate structure intersecting the second active region and the second channel layer, a first source/drain region disposed on the first active region and contacting the plurality of first channel layers, and a second source/drain region and contacting the second channel layer. The plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.

Semiconductor transistor device including multiple channel layers with different materials

An integrated circuit device includes a fin-type active area along a first horizontal direction on a substrate, a device isolation layer on opposite sidewalls of the fin-type active area, a gate structure along a second horizontal direction crossing the first horizontal direction, the gate structure being on the fin-type active area and on the device isolation layer, and a source/drain area on the fin-type active area, the source/drain area being adjacent to the gate structure, and including an outer blocking layer, an inner blocking layer, and a main body layer sequentially stacked on the fin-type active area, and each of the outer blocking layer and the main body layer including a Si1−xGex layer, where x≠0, and the inner blocking layer including a Si layer.

A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.

Semiconductor device

Growing community of inventors

Suwon-si, South Korea

Seokhoon Kim