Samsung Electronics Co., Ltd.

Seokhan Park

Yoosang Hwang

Bong-Soo Kim

Kiseok Lee

Hui-Jung Kim

Kyunghwan Lee

Yongseok Kim

Jaeho Hong

Jiyoung Kim

Satoru Yamada

Hyuncheol Kim

Hunkook Lee

Taehun Kim

Boun Yoon

Jaekyu Lee

Sunghee Han

Dongoh Kim

Myeong-Dong Lee

Yanghee Lee

Ilyoung Yoon

Ilgweon Kim

Kijae Hur

Youngwoong Son

Seongjin Jeong

Youngsuk Lee

Jeehwan Heo

Seungho Han

Yejee Sunwoo

Woosong Ahn

Jaeyong Han

Junseop Lee

Sungchang Park

Bowon Yoo

A semiconductor device includes; cell transistors on a substrate, lower electrodes respectively connected to the cell transistors, arranged according to a first pitch in a first horizontal direction, and extending in a vertical direction, and an etching stop layer surrounding lower sidewalls of the lower electrodes and arranged at a level higher than a level of the cell transistors, wherein the etching stop layer includes a first portion vertically overlapping the lower electrodes and a second portion laterally surrounding the first portion, and the second portion includes recesses arranged according to a second pitch in the first horizontal direction.

Semiconductor device and manufacturing method

A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.

Semiconductor devices

A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.

Method of manufacturing semiconductor device

Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

Semiconductor memory devices

A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.

A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.

Semiconductor device with first and second data structures

An image sensor in which a pixel array and a memory cell array are merged includes a first semiconductor chip including the pixel array and the memory cell array in a same semiconductor chip, and a second semiconductor chip overlapping the first semiconductor chip in a vertical direction. The second semiconductor chip includes a first logic circuit that controls the pixel array, an analog-to-digital converter (ADC) that converts an analog signal output from the pixel array under control of the first logic circuit to a digital signal, and a second logic circuit that stores data that is output from the ADC circuit based on the digital signal to the memory cell array of the first semiconductor chip.

Image sensors in which pixel array and memory cell array are merged and electronic devices including the same

A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.

Semiconductor memory device and method of manufacturing the same

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Seongnam-si, South Korea

Seokhan Park