Electronics and Telecommunications Research Institute

Korea Telecommunication Authority

Seok Y Kang

Bheom Soon Joo

Bhum Cheol Lee

Kwang Joon Kim

Jung Sik Kim

Kwon Chul Park

Hye Young Kim

Hyuek Jae Lee

Bheom C Lee

An apparatus for enhancing the extinction ratio in an optical NRZ-to-RZ converting system, and an optical modulation system, are disclosed. The extinction ratio is improved by using an optical fiber loop mirror together with optical amplifiers. The apparatus for enhancing the extinction ratio includes a variable coupling means for receiving external signals to split them to respective terminals of a loop mirror. A variable optical delaying means delays the phases of the signals after their dispersion by the variable coupling means. An optical amplifying means positioned asymmetrically smaller than a bit time of an RZ signal pattern inputted slightly departed from the center of the loop mirror amplifies the optical intensity, and varies the refractive index so as to cause a phase delay. A polarization adjusting means adjusts the polarization of the optical signals, and an optical band pass filtering means removes noises from signals outputted from the loop mirror. The apparatus is used in an optical NRZ-to-RZ converting system.

Apparatus for enhancing extinction ratio in optical NRZ-to-RZ converting

This invention relates to an apparatus for retiming digital data transmitted at a high speed even though the phase of a binary data bit is not related to the phase of the static offset of a retiming clock pulse, the apparatus comprising: local clock pulse generation means 11 for generating and outputting local clock pulse FT; delayed clock pulse parallel generation means 12 for outputting, in parallel, n delayed clock pulses delayed sequentially by one cycle of local clock pulse FT; input data transition detection means 13 for outputting pulse DT each time the rising and falling carrier waves intersect in input data D; sequential logic parallel phase detection means 14 for providing clock pulse selection data by outputting sequential logic phases of the upper location of the pulse generated during input data transition and transition location of n delayed clock pulses; retiming clock pulse selection means 15 for outputting a retiming clock pulse according to the clock pulse selection data of the input delayed clock pulses; time delay compensation means 16 for outputting delayed input data; and data retiming means 17 for outputting the data retimed DR according to the retiming clock pulse.

Apparatus for retiming digital data transmitted at a high speed

A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass filter (integrator) for outputting a voltage of a low frequency component to the VCO in response to an output of the phase difference output controller and an output of the frequency comparator gain limiter, and a frequency-divider for frequency-dividing the clock pulse from the VCO at a desired ratio.

High-speed bit synchronizer with multi-stage control structure

Growing community of inventors

Daejeon, South Korea

Seok Y Kang