Samsung Electronics Co., Ltd.

Seok-Woo Choi

Yang-Ki Kim

Hae-young Chung

A delay locked loop circuit is disclosed. The circuit includes a phase detector for comparing the phase of an input clock signal with the phase of a feedback clock signal that is fed back into the phase detector, and for outputting a detection signal. The circuit also includes a control circuit unit for controlling a delay line in response to the detection signal, a delay line for delaying the input clock by a predetermined amount of delay in response to output impedance calibration codes applied to the delay line, and a replica circuit configured to have the same delay conditions as those of an actual clock path to a circuit of the semiconductor device, to receive a delay clock signal of the delay line, and to generate the feedback clock signal.

Delay locked loop circuit including delay line with reduced sensitivity to variation in PVT

A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.

Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads

A transceiver system includes a first semiconductor device having a first input/output (I/O) pad connected with an I/O channel and a second semiconductor device having a second I/O pad connected with the I/O channel. The first semiconductor device is configured to terminate the first I/O pad with a first voltage when data is received, and maintain the first I/O pad and the I/O channel at the first voltage when data is transmitted. The second semiconductor device is configured to terminate the second I/O pad with a second voltage higher than the first voltage when data is received, and maintain the second I/O pad and the I/O channel at the second voltage when data is transmitted.

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Seoul, South Korea

Seok-Woo Choi