Samsung Electronics Co., Ltd.

Seok-Won Hwang

Dong-Ho Hyun

Woo-Jin Lee

Young-Uk Chang

Chang-sik Kim

Hyun-Dong Kim

Dong-ryul Ryu

Young-uk Chang

Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may be connected to respective first on-die termination circuits that may not be tested, and the second output nodes may be connected to second on-die termination circuits that may be tested. The semiconductor memory device may be configured to generate test signals of the second on-die termination circuits and to provide the test signals to the second output nodes. The coupling circuit may be configured to connect the first output nodes and the second output nodes to communication channels, respectively. The tester may be configured to test a logic state of the test signals of the communication channels.

Memory test system including semiconductor memory device suitable for testing an on-die termination, and method thereof

A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.

Semiconductor device, test system and method of testing on die termination circuit

An integrated circuit memory device may include a memory cell array, a plurality of data input/output pins, and a plurality of input/output circuits coupled to respective data input/output pins. The input/output circuits may be configured to accept respective data bits being written to the memory cell array from the respective data input/output pins during a write operation, and the input/output circuits may be configured to provide respective data bits being read from the memory cell array to the respective data input/output pins during a read operation. In addition, the input/output circuits may be configured to modify operational characteristics thereof responsive to respective control bits received through the respective data input/output pins during a mode set operation. Related methods and systems are also discussed.

Methods of modifying operational characteristic of memory devices using control bits received through data pins and related devices and systems

An integrated circuit memory device includes a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and is configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device. Related methods are also disclosed.

Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device

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Seoul, South Korea

Seok-Won Hwang