Samsung Electronics Co., Ltd.

Seok-Won Ahn

Dong Jin Kim

JaePhil Kong

Myung-Suk Choi

Hwa-seok Oh

Hyeonwu Kim

Yongwon Cho

Chanho Yoon

Chan-Ho Yoon

Chan Ho Yoon

Kil Hwan Kim

Jae Phil Kong

Kwang Ho Yoo

Daekyoung Kim

Hyeon-Wu Kim

Hyun-Ju Yi

Eun Cheol Kim

A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

Storage device having wide input/output and method of operating the same

A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.

Storage device for performing map scheduling and electronic device including the same

A memory controller is used to control a first storage block having a first data rate and a second storage block having a second data rate. The memory controller includes; a memory interface that transceives a data signal and a data strobe signal with the first and second storage blocks, and a sub controller that stores access information about the first data rate and the second data rate. The sub controller may include a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block.

Storage device including multi data rate memory device and memory controller

A data storage device is provided. The data storage device includes a storage medium configured to store data blocks included in a stripe set, and a controller connected to the storage medium and configured to, decode a first data block disposed in a column among the data blocks, during a read operation of the first data block, and read first group data blocks disposed in the column among the data blocks, based on a read failure of the first data block.

Raid-6 data storage device and data processing system including the same

A non-volatile memory system includes a memory controller, where the memory controller includes a first region including a first memory that stores compressed code, and a second region including a second memory that stores decompressed code. Power supplied to the first region and the second region is controlled according to an operation mode of the non-volatile memory system.

Non-volatile memory system, memory card having the same, and operating method of non-volatile memory system

A non-volatile memory and a method of controlling an erase operation of the non-volatile memory using a controller are provided. The method of controlling the erase operation includes beginning performance of the erase operation, monitoring a next command to be performed in the non-volatile memory while performing the erase operation, determining an erase status, and continuing, suspending or canceling the erase operation based on the determination result of the erase status.

Method of controlling erase operation of a memory and memory system implementing the same

An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.

Error correction code block having dual-syndrome generator, method thereof, and system having same

Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data.

Growing community of inventors

Suwon-si, South Korea

Seok-Won Ahn