Dongbu Electronics, Co. Ltd.

Dongbu Anam Semiconductor, Inc.

Seok Su Kim

Chee Hong Choi

Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

Methods for fabricating semiconductor devices

A method for manufacturing a semiconductor device includes forming a first insulating layer on a semiconductor substrate having a semiconductor chip region and a scribe region; forming a mask pattern on the first insulating layer; removing portions of the first insulating layer using the mask pattern so as to form a contact hole in the semiconductor chip region and a scribe region opening exposing the scribe region; forming a metal contact plug in a contact hole and a metal sidewall on a side of the first insulating layer in the scribe region opening; forming a metallization wiring on the first insulating layer; and forming a second insulating layer and a protective layer over the metal contact plug and the metal sidewall so as to cover the semiconductor chip region and the scribe region.

Semiconductor device and method for manufacturing the same

Methods of fabricating a semiconductor device is disclosed. An illustrated method comprises: providing a substrate including an active region and a non-active region; forming a first gate electrode including a dielectric layer pattern, a first conducting layer pattern, and an insulating layer pattern; growing a thermal oxide layer on the substrate and the first gate electrode; forming a nitride layer over the substrate and the thermal oxide layer; and removing the nitride layer and the thermal oxide layer using an etch back process to form spacers on sidewalls of the first gate electrode. By including the thermal oxide layer, the spacers ensure insulation capability.

Methods for fabricating a semiconductor device

Semiconductor devices and methods for fabricating a silicide of a semiconductor device are disclosed. An illustrated method comprises: forming a gate electrode; depositing an insulating layer; removing a predetermined portion of the insulating layer in order to expose a portion of the gate electrode; forming silicide on the exposed portion of the gate electrode; and etching the insulating layer while using the silicide as an etching mask.

Method of forming a semiconductor device using a silicide etching mask

Methods of fabricating semiconductor devices are disclosed. An example method may include providing a substrate including an active region and a non-active region and forming a first gate electrode comprising a dielectric layer pattern, a first conducting layer pattern, and a first insulating layer pattern, the first gate electrode functioning as a flash memory. The example method may also include forming spacers on sidewalls of the first gate electrode; forming a second gate electrode comprising a gate oxide, a second conducting layer pattern, and a second insulating layer pattern, the second gate electrode functioning as a normal gate electrode; and removing a residual conducting layer on one sidewall of the spacer.

Method of fabricating a semiconductor device that includes removing a residual conducting layer from a sidewall spacer corresponding to a gate electrode of a flash memory

A method of fabricating a mask ROM comprising: preparing a substrate defined by a memory cell array region and a peripheral region; forming a device isolation film between the memory cell array region and the peripheral region; forming a gate-forming material layer; covering the memory cell array region and selectively etching the gate-forming material layer in the peripheral region to form a first gate; forming an insulation spacer in a lateral portion of the gate; injecting ion to the substrate in the peripheral region to form a source/drain region; forming salicide on the gate-forming material layer of the memory cell array region and the gate and in the source/drain region; covering the peripheral region and selectively etching the gate-forming material layer in the memory cell array region to form a second gate; and forming a protective film on the resultant substrate.

Growing community of inventors

Gyeonggi-do, South Korea

Seok Su Kim