Samsung Electronics Co., Ltd.

Seok-Jun Ko

Hyung-Jin Choi

Pan-Soo Kim

Jung-Hyun Lee

Kyung-Ha Lee

Jae-wook Lee

An asymmetric error correction apparatus and method, and clock recovering apparatus and data recovering apparatus for a system for reading data from an optical recording medium such as a CD or DVD that has a multi-level input signal and irregular characteristic of zero-crossing transition. The signal inputted from the optical recording medium is digitized, and a zero-crossing detector extracts four sequential samples and detects a zero-crossing point from the two intermediate samples. An asymmetric error detector judges an asymmetric state and asymmetric polarity of the digital signal from a sum of the two side samples among the four samples if the zero-crossing point is detected. A correction section accumulates the judged asymmetric polarities, judges an asymmetric error of the digital signal if the accumulated value exceeds a predetermined threshold, and corrects the asymmetric error of the read signal caused by an inaccurate pit length.

Asymmetric error correction apparatus and method, and clock recovering apparatus for optical reading system employing the same

An apparatus for detecting a phase error for a system such as a CD or a DVD having a multi-level input signal with an irregular zero crossing shift, and a phase locked loop circuit using the same. An A/D converter digitizes a signal read from the CD or the DVD. A phase error detect unit detects a zero crossing of the digital signal consecutively input from the A/D converter, and detects a timing error from a signal corresponding to the detected zero crossing. An error correction unit corrects a sampling timing error of the A/D converter by shifting a phase corresponding to the timing error input from the phase error detect unit. An apparatus for detecting a timing error having a tracking function reduces the amount of normal jitter and a dispersion value of the timing error in accordance with a signal to noise ratio.

Apparatus for detecting phase error by using zero crossing characteristics of input signal, and phase locked loop circuit using the same

A channel compensator for estimating and for compensating a phase change and a residual frequency offset of a despreaded signal, prior to synchronous demodulation in a DS-CDMA receiver. In the channel compensator, a first integrator accumulates input signals sampled at a given chip rate for a predetermined period and multiplies the accumulated value by a given gain. A shift register having a plurality of registers shifts the data output from the first integrator. A second integrator integrates the data generated at once from the respective registers of the shift register. A delay means delays the input signal for a predetermined time, and a multiplier multiplies the delayed input signal by an output of the second integrator in order to generate the compensated signal. The delay device delays the input signal by a time required for the input signal to reach a central register of the shift register through the first integrator. The second integrator includes a summer means for summing the values of the respective registers of the shift register at an update period of the first integrator, and a multiplier for multiplying a value output from the summer means by a reciprocal number of the number of the registers to reduce the dispersion of an estimation value due to noises, and for adjusting a bit value for detected information.

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Suwon, South Korea

Seok-Jun Ko