Skhynix Inc.

Sk Hynik Inc.

Seok Joon Kang

Ho Seok Em

Jun Ho Cheon

Moo Hui Park

Jin Su Park

Jae Jin Lee

Chang Sik Yoo

Chun Seok Jeong

Jang Woo Lee

Hoon Moo Choi

Sang Don Lee

Chang Yong Ahn

Yeon Uk Kim

A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Nonvolatile memory apparatus for mitigating read disturbance and system using the same

A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Nonvolatile memory apparatus for performing a read operation and a method of operating the same

A non-volatile memory apparatus includes a memory cell coupled between a global bit line and a global word line. A bit line control circuit configured to apply a bit line read bias voltage to the global bit line based on a read signal. A snap-back detection circuit coupled to the global word line, and configured to generate a data output signal and a current enable signal by detecting a snap-back of the memory cell. A word line control circuit configured to apply a word line read bias voltage to the global word line based on the read signal, and may increase an amount of a current flowing through the memory cell based on the current enable signal.

Nonvolatile memory apparatus for mitigating snap-back disturbance, and read and write method of the nonvolatile memory apparatus

A semiconductor system may include a memory controller and a non-volatile memory apparatus. The memory controller may generate a recovery command signal by measuring a power off time of the non-volatile memory apparatus. The non-volatile memory apparatus may perform a drift recovery operation based on the recovery command signal.

Nonvolatile memory apparatus, semiconductor system including the nonvolatile memory apparatus, and operating method of the nonvolatile memory apparatus

A test circuit block may include a first signal line, a second signal line, a high resistive path unit, and a low resistive path unit. The high resistive path unit may be connected between the first signal line and the second signal line. The low resistive path unit may have a resistance lower than that of the high resistive path unit. The low resistive path unit may be selectively connected in parallel with the high resistive path unit between the first signal line and the second signal line.

Test circuit block, variable resistance memory device including the same, and method of forming the variable resistance memory device

A sense amplifier may be provided. The sense amplifier may include an amplification circuit and/or a cell current control circuit. The amplification circuit may be configured to compare a voltage level of a signal line with a level of a read voltage. The cell current control circuit may be configured to decrease the voltage level of the signal line based on an output signal.

Sense amplifier, memory apparatus and system including the same

A resistive memory device and a method may be provided. The resistive memory device may include a reset voltage-detecting circuit, a set voltage-detecting circuit, a control circuit and a read voltage-generating circuit. The reset voltage-detecting circuit may receive a variable preliminary reset current to detect reference reset voltage information. The set voltage-detecting circuit may receive a variable preliminary set current to detect reference set voltage information. The control circuit may receive the reference reset voltage information and the reference set voltage information to determine middle voltage information of the reference reset voltage information and the reference set voltage information. The read voltage-generating circuit may receive the middle voltage information to generate a read voltage.

Resistive memory device and method relating to a read voltage in accordance with variable situations

A current driver may include a current applying circuit and a current adjusting circuit. The current applying circuit may include a threshold switching element, and may provide unlimited amount of current while occupying small circuit area therefor. The current adjusting circuit may provide a bias voltage and control an amount of the current provided from the current applying circuit.

Current driver, write driver, and semiconductor memory apparatus using the same

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.

Sense amplifier for high speed sensing, memory apparatus and system including the same

An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.

Analog capacitor

A semiconductor integrated circuit device configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The semiconductor integrated circuit device may include a leakage current sensing unit configured for sensing a pure leakage current of a cell array, and a determination circuit unit configured for comparing a voltage level of the input node with a reference voltage and for determining a state of read data while in a read mode. Whereby an output current may be compared with a read current of the cell array at the input node, and the output current may include the summation of the pure leakage current and a reference current.

Semiconductor integrated circuit device including a leakage current sensing unit and method of operating the same

A semiconductor integrated circuit device and a system including the same, configured for sensing a pure leakage current of a cell array and improving a read error is disclosed. The system a controller and a memory configured to interface with the controller. The memory includes a semiconductor integrated circuit device includes a leakage current sensing unit configured to sense a pure leakage current of a cell array according to a command of the controller; and a determination circuit unit configured to compare a voltage level of an input node with a reference voltage and determine a state of read data while in a read mode. The voltage level of the input node is decided by comparing an output current and a read current and the output current is decided by summing the pure leakage current and a reference current.

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Seoul, South Korea

Seok Joon Kang